SN74BCT2414_16 Datasheet, PDF (7/14 Pages) Texas Instruments – MEMORY DECODER WITH ON-CHIP SUPPLY VOLTAGE MONITOR

SN74BCT2414
MEMORY DECODER
WITH ONĆCHIP SUPPLY VOLTAGE MONITOR
SCBS059B − MARCH 1989 − REVISED NOVEMBER 1993
APPLICATION INFORMATION
A typical application circuit for a battery-buffered memory in a microcomputer system is shown in Figure 1 which uses
the SN74BCT2414. When power fails, the supply-voltage supervisor (TL7705) resets the microcomputer and
disables the memory by switching the shutdown input SD of the memory decoder to a logic zero. All memory decoder
outputs are forced to a logic one. Abnormal write commands from the microprocessor, which may be issued during
further voltage breakdown, no longer affect the contents of the memory. When the system supply voltage becomes
lower than approximately 3.65 V, the voltage monitor inside the SN74BCT2414 memory decoder disconnects the
input buffers of this circuit from the decoding logic internally and keeps all outputs at a logic one. The VS output is
also switched off, disconnecting the system supply voltage from the memory circuits. During this low-voltage
condition, the memory decoder and the memory circuits are supplied by the battery.
Microprocessor
D0 − D7
A0 − A15
8
VCC
D3 _R3
DBIN
WE
RESET
16
R1
Q1
R2 1 kΩ
D1
1N4148
5V
TL7705A
10 kΩ
VCC
SENSE
RES
RESIN
VREF
Ct _GND
0.1 µF
0.1 µF
SN74BCT2414
VS
A15
1G
2G
A14
1B
2B
A13
1A
2A
SD
G
VCC
Vbat
1Y0
1Y1
1Y2
1Y3
2Y0
2Y1
2Y2
2Y3
CE
A0 − A12
OE
WR
For further information on this device, please contact factory.
8- × 8K-Byte CMOS RAM
Figure 1. Memory System With Battery Backup
VCC
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
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