SN54125_15 Datasheet, PDF (7/23 Pages) Texas Instruments – QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS

The SN54125, SN54126, SN74125,
SN74126, and SN54LS126A are
obsolete and are no longer supplied.
SN54125, SN54126, SN54LS125A, SN54LS126A,
SN74125, SN74126, SN74LS125A, SN74LS126A
QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SDLS044A – DECEMBER 1983 – REVISED MARCH 2002
Test
Point
From Output
Under Test
CL
(see Note A)
PARAMETER MEASUREMENT INFORMATION
SERIES 54/74 DEVICES
VCC
VCC
RL
(see Note B)
VCC
From Output
Under Test
CL
(see Note A)
RL
Test
Point
From Output
Under Test
CL
(see Note A)
Test RL
Point
1 kΩ
S1
(see Note B)
S2
LOAD CIRCUIT
FOR 2-STATE TOTEM-POLE OUTPUTS
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
High-Level
Pulse
Low-Level
Pulse
1.5 V
tw
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
Timing
Input
tsu
Data
Input
3V
1.5 V
0V
th
1.5 V
3V
1.5 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Input
1.5 V
3V
1.5 V
0V
tPLH
In-Phase
Output
(see Note D)
1.5 V
tPHL
VOH
1.5 V
VOL
tPHL
tPLH
Out-of-Phase
Output
(see Note D)
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOH
VOL
Output
Control
(low-level
enabling)
tPZL
1.5 V
3V
1.5 V
0V
tPLZ
Waveform 1
(see Notes C
and D)
tPZH
Waveform 2
(see Notes C
and D)
1.5 V
1.5 V
≈1.5 V
VOL ^{VOL + 0.5 V}
tPHZ
VOH
VOH – 0.5 V
≈1.5 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. All diodes are 1N3064 or equivalent.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL.
E. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω; tr and tf ≤ 7 ns for Series
54/74 devices and tr and tf ≤ 2.5 ns for Series 54S/74S devices.
F. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
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