P82B715_16 Datasheet, PDF (7/22 Pages) Texas Instruments – I2C Bus Extender

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8 Detailed Description
P82B715
SCPS145B – DECEMBER 2007 – REVISED FEBRUARY 2016
8.1 Overview
The I²C bus capacitance limit of 400 pF restricts practical communication distances to a few meters. One of the
advantages of the P82B715 is that it can isolate bus capacitance such that the total loading (devices,
connectors, traces and wires) of the new bus or remote I²C nodes are not apparent to other I²C buses (or
nodes). This is achieved by using one P82B715 device at each end of a long cable. The pin Lx of one P82B715
device must be connected to Lx of the second P82B715 (similarly for Ly). This allows the total system
capacitance load to be around 3000 pF. The P82B715 uses unidirectional analog current amplification to
increase the current sink capability of I²C chips to change the 400-pF I²C bus specification limit into a 3-nF bus
wiring capacitance limit. That means longer cables or lower-cost general-purpose wiring may be used to connect
two separate I²C-based systems, without worrying about the special voltage levels associated with other I²C bus
buffers.
Multiple P82B715s can be connected together in a star or multipoint architecture by their Lx/Ly ports, without
limit, as long as the total capacitance of the system remains less than about 3000 pF (400 pF or less when
referenced to any Sx/Sy connection). In that arrangement, the master and/or slave devices are attached to the
Sx/Sy port of each P82B715. In normal use, the power-supply voltages at each end of the low-impedance
buffered bus line should be the same. If these differ by a significant amount, noise margin is sacrificed.
Two or more Sx or Sy I/Os can be interconnected and are also fully compatible with bus buffers that use voltage-
level offsets (such as the TCA9517) because it duplicates and transmits the offset voltage.
8.2 Functional Block Diagram
V_CC
Sx/SDA
P82B715
Buffer
Lx/LDA
Sy/SCL
Buffer
Ly/LCL
GND
8.3 Feature Description
8.3.1 Sx and Sy
The I²C pins (Sx and Sy) are designed to interface with a normal I²C bus. The maximum I²C bus supply voltage
is 12 V. The Sx and Sy pins contain identical circuitry and can be used interchangeably as SCL or SDA.
8.3.2 Lx and Ly
The Lx and Ly pins are designed to interface with the high capacitance bus. This port of the device features
circuitry to assist in sinking large amounts of currents required to operate a large capacitance bus at high
speeds. More on this circuitry can be found in Lx/Ly Buffered Bus Circuitry.
8.3.3 Lx/Ly Buffered Bus Circuitry
On the special low-impedance or buffered-line side, the corresponding output becomes the LDA data line or LCL
clock line. The P82B715 provides current amplification from its I²C bus to its low impedance or buffered bus.
Whenever current is flowing out of Sx into an I²C chip driving the I²C bus low, its amplifier sinks ten times that
current into Lx, to drive the buffered bus low (see Figure 3). To minimize interference and ensure stability, the
current rise and fall times of the Lx drive amplifier are internally controlled. The P82B715 does not amplify signal
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