LP3943 Datasheet, PDF (7/21 Pages) National Semiconductor (TI) – RGB/White/Blue 16-LED Fun Light Driver

LP3943
www.ti.com
SNVS256A – MAY 2004 – REVISED MAY 2004
Electrical Characteristics (continued)
Unless otherwise noted, V_DD = 5.5V. Typical values and limits appearing in normal type apply for T_J = 25°C. Limits appearing
in boldface type apply over the entire junction temperature range for operation, T_J = −40°C to +125°C. ⁽¹⁾
Symbol
Parameter
Conditions
Typical
Limit
Min Max
Units
t_TRANS
Maximum Pulse Width of Spikes ⁽³⁾
that Must Be Suppressed by the
Input Filter of Both DATA & CLK
Signals
50
ns
Typical Performance Characteristics
Frequency vs. Temp
(T_A = −40°C to +85°C),
V_DD = 2.3V to 3.0V
10
5
0
-5
-10
-40 -20 0 20 40 60 80
TEMPERATURE (°C)
Application Notes
THEORY OF OPERATION
The LP3943 takes incoming data from the baseband controller and feeds them into several registers that control
the frequency and the duty cycle of the LEDs. Two prescaler registers and two PWM registers provide two
individual rates to dim or blink the LEDs (for more information on these registers, refer to Table 3). Each LED
can be programmed in one of four states—on, off, DIM0 rate or DIM1 rate. Two read-only registers provide
status on all 16 LEDs. The LP3943 can be used to drive RGB LEDs and/or single-color LEDs to create a colorful,
entertaining, and informative setting. Alternatively, it can also drive RGB LED as a flashlight. This is particularly
suitable for accessory functions in cellular phones and toys. Any LED pins not used to drive LED can be used for
General Purpose Parallel Input/Output (GPIO) expansion.
The LP3943 is equipped with Power-On Reset that holds the chip in a reset state until V_DD reaches V_POR during
power up. Once V_POR is achieved, the LP3943 comes out of reset and initializes itself to the default state.
To bring the LP3943 into reset, hold the RST pin LOW for a period of TW. This will put the chip into its default
state. The LP3943 can only be programmed after RST signal is HIGH again.
I²C DATA VALIDITY
The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of
the data line can only be changed when CLK is LOW.
Copyright © 2004, Texas Instruments Incorporated
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