ISO7242ADWRG4 Datasheet, PDF (7/21 Pages) Texas Instruments – 1-Mbps QUAD DIGITAL ISOLATORS

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Not Recommended for New Designs
ISO7240A
ISO7241A
ISO7242A
SLLS905E – MAY 2008 – REVISED JANUARY 2010
ELECTRICAL CHARACTERISTICS: V_CC1 and V_CC2 at 3.3 V⁽¹⁾ OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
SUPPLY CURRENT
ISO7240A
Quiescent
1 Mbps
V_I = V_CC or 0 V, all channels, no load, EN₂ at 3 V
I_CC1
ISO7241A
ISO7242A
ISO7240A
Quiescent
1 Mbps
Quiescent
1 Mbps
Quiescent
1 Mbps
V_I = V_CC or 0 V, all channels, no load, EN₁ at 3 V,
EN₂ at 3 V
V_I = V_CC or 0 V, all channels, no load, EN₁ at 3 V,
EN₂ at 3 V
V_I = V_CC or 0 V, all channels, no load, EN₂ at 3 V
I_CC2
ISO7241A
Quiescent
1 Mbps
ISO7242A
Quiescent
1 Mbps
ELECTRICAL CHARACTERISTICS
V_I = V_CC or 0 V, all channels, no load, EN₁ at 3 V,
EN₂ at 3 V
V_I = V_CC or 0 V, all channels, no load, EN₁ at 3 V,
EN₂ at 3 V
I_OFF
Sleep mode output current
V_OH
High-level output voltage
V_OL
Low-level output voltage
V_I(HYS)
I_IH
I_IL
C_I
CMTI
Input voltage hysteresis
High-level input current
Low-level input current
Input capacitance to ground
Common-mode transient immunity
EN at 0 V, single channel
I_OH = –4 mA, See Figure 1
I_OH = –20 mA, See Figure 1
I_OL = 4 mA, See Figure 1
I_OL = 20 mA, See Figure 1
IN from 0 V or V_CC
IN at V_CC, V_I = 0.4 sin (4E6pt)
V_I = V_CC or 0 V, See Figure 4
V_CC – 0.4
V_CC – 0.1
–10
25
(1) For the 5-V operation, V_CC1 or V_CC2 is specified from 4.5 V to 5.5 V.
For the 3-V operation, V_CC1 or V_CC2 is specified from 3.15 V to 3.6 V.
TYP MAX
0.5 1
1
2
4
7
4
7
6 10
6 10
9.5 15
10 15
8 13
8 13
6 10
6 10
0
0.4
0.1
150
10
2
50
UNIT
mA
mA
mA
mA
mA
V
V
mV
mA
pF
kV/ms
SWITCHING CHARACTERISTICS: V_CC1 and V_CC2 at 3.3-V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
t_PLH, t_PHL
PWD
Propagation delay
Pulse-width distortion |t_PHL – t_PLH|⁽¹⁾
See Figure 1
t_sk(o)
Channel-to-channel output skew ⁽²⁾
t_r
Output signal rise time
t_f
Output signal fall time
See Figure 1
t_PHZ
Propagation delay, high-level-to-high-impedance output
t_PZH
Propagation delay, high-impedance-to-high-level output
See Figure 2
t_PLZ
Propagation delay, low-level-to-high-impedance output
t_PZL
Propagation delay, high-impedance-to-low-level output
t_fs
Failsafe output delay time from input power loss
See Figure 3
MIN TYP MAX UNIT
45
110
ns
12
3.5
0
1
ns
2
2
15 20
15 20
ns
15 20
15 20
18
ms
(1) Also referred to as pulse skew.
(2) t_sk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
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