ISO721-Q1_16 Datasheet, PDF (7/27 Pages) Texas Instruments – AND/OR 5-V HIGH-SPEED DIGITAL ISOLATORS

ISO721-Q1, ISO722-Q1
www.ti.com
SLLS918C – JULY 2008 – REVISED JUNE 2013
ELECTRICAL CHARACTERISTICS: V_CC1 at 3.3-V, V_CC2 at 5-V⁽¹⁾ OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
Quiescent
I_CC1
V_CC1 supply current
25 Mbps
V_I = V_CC or 0 V, No load
ISO722-Q1
Sleep Mode
I_CC2
V_CC2 supply current
Quiescent
V_I = V_CC or 0 V, No load
EN at V_CC
EN at 0 V or ISO721-
Q1
V_OH
V_OL
V_I(HYS)
I_IH
I_IL
I_OZ
25 Mbps
High-level output voltage
Low-level output voltage
Input voltage hysteresis
High-level input current
Low-level input current
High-impedance output
current
ISO722-Q1
V_I = V_CC or 0 V, No load
I_OH = –4 mA, See Figure 1
I_OH = –20 μA, See Figure 1
I_OL = 4 mA, See Figure 1
I_OL = 20 μA, See Figure 1
IN at 2 V
IN at 0.8 V
EN, IN at V_CC
V_CC – 0.8
V_CC – 0.1
–10
C_I
Input capacitance to ground
IN at V_CC, V_I = 0.4 sin (4E6πt)
CMTI
Common-mode transient immunity
V_I = V_CC or 0 V, See Figure 5
15
TYP MAX UNIT
0.3 0.5
mA
1
2
200 μA
8 12
mA
10 14
4.6
V
5
0.2 0.4
V
0 0.1
150
mV
10 μA
μA
1 μA
1
pF
40
kV/μs
(1) For 5-V operation, V_CC1 or V_CC2 specification is from 4.5 V to 5.5 V. For 3.3-V operation, V_CC1 or V_CC2 specification is from 3 V to 3.6 V.
SWITCHING CHARACTERISTICS: V_CC1 at 3.3-V, V_CC2 at 5-V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
t_PLH
t_PHL
t_sk(p)
t_sk(pp)
(1)
Propagation delay, low-to-high-level output
Propagation delay , high-to-low-level output
Pulse skew |t_PHL – t_PLH|
Part-to-part skew
See Figure 1
See Figure 1
See Figure 1
MIN TYP MAX UNIT
17 30 ns
17 30 ns
0.5 3 ns
0 5 ns
t_r
Output signal rise time
t_f
Output signal fall time
t_pHZ
Sleep-mode propagation delay,
high-level-to-high-impedance output
t_pZH
Sleep-mode propagation delay,
high-impedance-to-high-level output
ISO722-Q1
t_pLZ
Sleep-mode propagation delay,
low-level-to-high-impedance output
t_pZL
Sleep-mode propagation delay,
high-impedance-to-low-level output
t_fs
Failsafe output delay time from input power loss
t_jit(PP) Peak-to-peak eye-pattern jitter
See Figure 1
See Figure 1
See Figure 2
See Figure 3
See Figure 4
100-Mbps NRZ data input,
See Figure 6
100-Mbps unrestricted bit
run length data input, See
Figure 6
2
ns
2
ns
7 9 15 ns
4.5 5 8 μs
7 9 15 ns
4.5 5 8 μs
3
μs
2
ns
3
(1) t_sk(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
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