DS90LV001_15 Datasheet, PDF (7/21 Pages) Texas Instruments – 800 Mbps LVDS Buffer

DS90LV001
www.ti.com
Pin Name
GND
IN −
IN+
NC
V_CC
OUT+
OUT -
EN
DAP
Pin #
1
2
3
4
5
6
7
8
NA
SNLS067E – JANUARY 2001 – REVISED APRIL 2013
DS90LV001 Pin Descriptions (SOIC and WSON)
Input/Output
Description
P
Ground
I
Inverting receiver LVDS input pin
I
Non-inverting receiver LVDS input pin
No Connect
P
Power Supply, 3.3V ± 0.3V.
O
Non-inverting driver LVDS output pin
O
Inverting driver LVDS output pin
I
Enable pin. When EN is LOW, the driver is disabled and the LVDS outputs are in TRI-
STATE. When EN is HIGH, the driver is enabled. LVCMOS/LVTTL levels.
NA
Die Attach Pad or DAP (WSON Package only). The DAP is NOT connected to the
device GND nor any other pin. It is still recommended to connect the DAP to a GND
plane of a PCB for enhenced heat dissipation.
TYPICAL APPLICATIONS
Backplane Stub-Hider Application
Cable Repeater Application
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