DS90LT012AH_15 Datasheet, PDF (7/16 Pages) Texas Instruments – High Temperature 3V LVDS Differential Line Receiver

NRND
DS90LT012AH
www.ti.com
SNLS199A – SEPTEMBER 2005 – REVISED APRIL 2013
TERMINATION
The DS90LT012AH integrates the terminating resistor for point-to-point applications. The resistor value will be
between 90Ω and 133Ω.
THRESHOLD
The LVDS Standard (ANSI/TIA/EIA-644-A) specifies a maximum threshold of ±100mV for the LVDS receiver.
The DS90LV012A and DS90LT012A support an enhanced threshold region of −100mV to 0V. This is useful for
fail-safe biasing. The threshold region is shown in the Voltage Transfer Curve (VTC) in Figure 6. The typical
DS90LT012AH LVDS receiver switches at about −30mV. Note that with V_ID = 0V, the output will be in a HIGH
state. With an external fail-safe bias of +25mV applied, the typical differential noise margin is now the difference
from the switch point to the bias point. In the example below, this would be 55mV of Differential Noise Margin
(+25mV − (−30mV)). With the enhanced threshold region of −100mV to 0V, this small external fail-safe biasing of
+25mV (with respect to 0V) gives a DNM of a comfortable 55mV. With the standard threshold region of ±100mV,
the external fail-safe biasing would need to be +25mV with respect to +100mV or +125mV, giving a DNM of
155mV which is stronger fail-safe biasing than is necessary for the DS90LT012AH. If more DNM is required, then
a stronger fail-safe bias point can be set by changing resistor values.
Figure 6. VTC of the DS90LT012AH LVDS Receiver
FAIL SAFE BIASING
External pull up and pull down resistors may be used to provide enough of an offset to enable an input failsafe
under open-circuit conditions. This configuration ties the positive LVDS input pin to VDD thru a pull up resistor
and the negative LVDS input pin is tied to GND by a pull down resistor. The pull up and pull down resistors
should be in the 5kΩ to 15kΩ range to minimize loading and waveform distortion to the driver. The common-
mode bias point ideally should be set to approximately 1.2V (less than 1.75V) to be compatible with the internal
circuitry. Please refer to application note AN-1194, “Failsafe Biasing of LVDS Interfaces”(SNLA051) for more
information.
PROBING LVDS TRANSMISSION LINES
Always use high impedance (> 100kΩ), low capacitance (< 2 pF) scope probes with a wide bandwidth (1 GHz)
scope. Improper probing will give deceiving results.
CABLES AND CONNECTORS, GENERAL COMMENTS
When choosing cable and connectors for LVDS it is important to remember:
Use controlled impedance media. The cables and connectors you use should have a matched differential
impedance of about 100Ω. They should not introduce major impedance discontinuities.
Balanced cables (e.g. twisted pair) are usually better than unbalanced cables (ribbon cable, simple coax) for
noise reduction and signal quality. Balanced cables tend to generate less EMI due to field canceling effects and
also tend to pick up electromagnetic radiation a common-mode (not differential mode) noise which is rejected by
the receiver.
For cable distances < 0.5M, most cables can be made to work effectively. For distances 0.5M ≤ d ≤ 10M, CAT 3
(category 3) twisted pair cable works well, is readily available and relatively inexpensive.
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