DS36954_16 Datasheet, PDF (7/19 Pages) Texas Instruments – Quad Differential Bus Transceiver

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DS36954
SNLS077C – JULY 1998 – REVISED APRIL 2013
Figure 8. Driver Enable and Disable Timing (t_PZL, t _PLZ)
(1)
(2)
(1) The input pulse is supplied by a generator having the following characteristics: f = 1.0 MHz, 50% duty cycle, trand tf <
6.0 ns, ZO = 50Ω.
(2) C_L includes probe and stray capacitance.
Figure 9.
Figure 10. Receiver Differential Propagation Delay Timing
(1)
(4)
(3)
(2)
(1) The input pulse is supplied by a generator having the following characteristics: f = 1.0 MHz, 50% duty cycle, trand tf <
6.0 ns, ZO = 50Ω.
(2) C_L includes probe and stray capacitance.
(3) Diodes are 1N916 or equivalent.
(4) On transceivers 1–3 the driver is loaded with receiver input conditions when DE/RE is high. Do not exceed the
package power dissipation limit when testing.
Figure 11.
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