DAC813 Datasheet, PDF (7/16 Pages) Burr-Brown (TI) – Microprocessor-Compatible 12-BIT DIGITAL-TO-ANALOG CONVERTER

gain error. The reference output may be used to drive
external loads, sourcing at least 5mA. This current should be
constant, otherwise the gain of the converter will vary.
POWER SUPPLY SENSITIVITY
Power supply sensitivity is a measure of the effect of a
power supply change on the D/A converter output. It is
defined as a ppm of FSR output change per percent of
change in either +V_CC or –V_CC about the nominal voltages
expressed in ppm of FSR/%. The first performance curve on
page 5 shows typical power supply rejection versus power
supply ripple frequency.
OPERATION
DAC813 is a complete single IC chip 12-bit D/A converter.
The chip contains a 12-bit D/A converter, voltage reference,
output amplifier, and microcomputer-compatible input logic
as shown in Figure 1.
INTERFACE LOGIC
Input latches hold data temporarily while a complete 12-bit
word is assembled before loading into the D/A latch. This
double-buffered organization prevents the generation of spu-
rious analog output values. Each latch is independently
addressable.
All latches are level-triggered. Data present when the con-
trol signals are logic “0” will enter the latch. When any one
of the control signals returns to logic “1”, the data is latched.
A truth table for the control signals is presented in Table II.
WR LLSB LMSB LDAC RESET
OPERATION
1
X
X
X
1
No operation
X
X
X
X
0
0
1
0
1
1
D/A latch set to 800_HEX
Enables 4 MSBs input latch
0
0
1
1
1
Enables 8 LSBs input latch
0
1
1
0
1 Loads D/A latch from input latches
0
0
0
0
1
Makes all latches transparent
“X” = Don’t Care
TABLE II. DAC813 Interface Logic Truth Table.
CAUTION: DAC813 was designed to use WR as the fast
strobe. WR has a much faster logic path than EN_X (or
LDAC). Therefore, if one permanently wires WR to DCOM
and uses only EN_X to strobe data into the latches, the
DATA HOLD time will be long, approximately 15ns to
30ns, and this time will vary considerably in this range
from unit to unit. DATA HOLD time using WR is 5ns max.
LOGIC INPUT COMPATIBILITY
The DAC813 digital inputs are TTL, 5V CMOS compat-
ible over the operating range of +V_CC. The input switching
threshold remains at the TTL threshold over the supply
range. An equivalent circuit of a digital input is shown in
Figure 2.
The logic input current over temperature is low enough to
permit driving the DAC813 directly from the outputs of 5V
CMOS devices.
Open DATA input lines will float to 7V or more. Although
this will not harm the DAC813, current spikes will occur in
the input lines when a logic 0 is asserted and, in addition,
WR 11
LMSB 14
LLSB 15
LDAC 12
Reset 13
MSB
LSB
D11
D8 D7
D0
28 27 26 25 24 23 22 21 20 19 18 17
V_L(1)
1
DCOM
16
4-Bit Latch
8-Bit Latch
12-Bit D/A Latch
12-Bit D/A Converter
49.5kΩ
+10V
Reference
0–800µA
24.9kΩ
25kΩ
25kΩ
4 BPO
2
20V
Range
3
20V
Range
9 V_OUT
NOTE: (1) V_L must be connected to +V_CC.
7
V_{REF IN}
6
V_{REF OUT}
5
ACOM
8
+V_CC
10
–V_CC
FIGURE 1. DAC813 Block Diagram.
7
®
DAC813