CC3000_16 Datasheet, PDF (7/19 Pages) Texas Instruments – Module – Wi-Fi 802.11b/g Network Processor

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Not Recommended For New Designs
CC3000
SWRS126 – NOVEMBER 2012
SPI HOST CONTROLLER INTERFACE
The SPI is the primary host interface to the CC3000 module.
The SPI interface contains the five-line, master and slave communication model shown in Figure 3.
MCU SPI
master
SPI_CLK
SPI_CS
SPI_IRQ
SPI_DOUT
SPI_DIN
CC3000
SPI slave
Figure 3. SPI Host Connectivity
SWRS126-016
Table 3 highlights the CC3000 SPI pin names and functions.
Table 3. SPI Line Description
Pin Name
SPI_CLK
SPI_CS ⁽¹⁾
SPI_DIN
SPI_IRQ ⁽²⁾
SPI_DOUT
Description
Clock (0 to 16 MHz) from host to slave
CS (active low) signal from host to slave
Data from host to slave
Interrupt from slave to host
Data from slave to host
(1) SPI_CS selects a CC3000 module, indicating that a master wants to communicate to the device.
(2) SPI_IRQ is a dual-purpose slave to the master direction line: in SPI IDLE state while no data transfer is active, driving SPI_IRQ low
indicates to the master that the CC3000 module has data to pass to it; driving SPI_IRQ low following SPI_CS deassertion indicates that
the CC3000 module is ready to receive data.
SPI Timing
Figure 4 shows the SPI timing sequence.
T_clk
T_p
SPI_CLK
(at device die)
SPI_DIN
(data from host to device)
SPI_DOUT
(data from device to host)
Host launch CC3000 capture CC3000 launch Host capture
t_is t_in
t_oh
t_os
Figure 4. SPI Timing Sequence
SWRS126-004
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