BQ77908 Datasheet, PDF (7/56 Pages) Texas Instruments – Stand-Alone Multi-Cell Lithium-Ion/Polymer Precision Protectors

bq77908
www.ti.com
SLUSAI5D – APRIL 2011 – REVISED NOVEMBER 2011
ELECTRICAL CHARACTERISTICS
Vcell(n) = 1.4 to 4.375 for all cells, T_A = –25°C to 85ºC, BAT = 5.6 to 35 V; Typical values stated where T_A = 25°C and BAT =
28.8 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
I_CC
I_{SHUTDOWN_2} ⁽¹⁾
Normal-mode average supply
current
Shutdown mode, LDO off
CHG, DSG = on (no dc load), VREG = on,
I_REG = 0 mA, BAT = 28.8 V
Vcell < Vuv, VREG = off (EEPROM set), CPCKN = 0.3 V
Vcell < Vuv, VREG = off (EEPROM set), CPCKN = 0.5 V
50
75
µA
5
17
µA
20
60
INTERNAL POWER CONTROL (STARTUP, SHUTDOWN, GATE DRIVE UNDERVOLTAGE)
V_STARTUP
Minimum voltage for initial power
up ⁽²⁾
Measured at BAT pin
7
V
V_POR ⁽³⁾
LDO POR voltage – voltage on
LDO that initiates a POR
I_LDO = 2 mA
2.7
3.2
V
V_{GATE_UV}
FET gate shutdown threshold
(voltage falling)
Measured at CCAP / DCAP pins
4.5
4.9
5.3
V
V_{GATE_UV_H}
FET DRIVE⁽⁴⁾
FET gate shutdown hysteresis
voltage
Measured at CCAP / DCAP pins
0.45
0.7
V
V_(FETON)
BAT voltage = 35 V (gate-drive circuit in regulation mode),
no dc load
11
12
14
Gate drive voltage at DSG and
CHG pins for FET ON (enabled)
conditions
BAT voltage = 10 V (gate-drive circuit in dropout mode), no
dc load
9
V
BAT voltage = 6.4 V (gate-drive circuit in dropout mode),
no dc load
>V_{GATE_UV}
V_(FETOFF)
Gate drive voltage at DSG and
CHG pins for FET OFF
(disabled) conditions
V_O(FETOFFDSG) = V_(DSG) – V_GND
V_O(FETOFFCHG) = V_(VHG) – V_pack–
0.2
V
0.2
t_r
Rise time, measured at IC pin
(CHG or DSG)
t_f
Fall time, measured at IC pin
(CHG or DSG)
VREG, INTEGRATED 3.3-V LDO
V_REG
Output-voltage regulation under
all line, load, temperature
conditions
I_SC
Short-circuit current limit
C_L = 50 nF, BAT = 35 V
C_L = 50 nF, BAT = 6.4 V
C_L = 50 nF, BAT = 35 V
C_L = 50 nF, BAT = 6.4 V
V_DSG: 10% to 90%
V_CHG: 10% to 90%
V_DSG: 10% to 90%
V_CHG: 10% to 90%
V_DSG : 90% to 10%
V_CHG: 90% to 10%
V_DSG : 90% to 10%
V_CHG: 90% to 10%
I_OUT = 10 mA (maximum dc load)⁽⁵⁾
I_OUT = 0.2 mA
VREG = 0 V, forced external short (thermally protected)⁽⁶⁾
90
140
90
140
µs
90
140
90
140
10
20
20
40
µs
50
100
50
100
3.1
3.3
3.55
V
3.1
3.3
3.55
V
20
45
mA
(1) For predictable shutdown current, the voltage at CPCKN with respect to VSS must be controlled. In the parallel FET case, CPCKN is
clamped through the body diode of the charge FET. In the series FET case, external circuitry is required to keep CPCKN from floating.
Contact TI for recommended application circuits.
(2) At this voltage, the LDO has sufficient voltage to maintain regulation. The POR then enables the charger-detect logic. Logic is held in
reset until inserted into charger and LDO has reached V_POR. The part still operates below 7 V to the spec limit of 5.6 V.
(3) V_POR and V_REG are derived from the same internal reference, so that the MAX value of VPOR and the MIN value of VREG do not occur
at the same time.
(4) FET drive is disabled if voltage at CCAP or DCAP pins < V_{GATE_UV}. Turnoff due to gate-drive undervoltage condition meets the same
timing requirements as logic-initiated gate turnoff.
(5) ELECTRICAL CHARACTERISTICS assume that I_OUT = 0 so that the internal junction temperature (TJ) is effectively equal to the
ambient temperature (T_A). For larger non-zero values of I_OUT, T_J can be significantly higher than T_A. In these cases, T_J should be
substituted for T_A in the test and operating conditions. T_J can be calculated from the device power dissipation as described under
THERMAL CHARACTERISTICS. The device power dissipation due to I_OUT is (VBAT – VREG) × I_OUT.
(6) Regulator shuts down prior to current-limit maximum specification if junction temperature exceeds safe range.
Copyright © 2011, Texas Instruments Incorporated
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