AFE5808A_17 Datasheet, PDF (7/83 Pages) Texas Instruments – 65-MSPS, 158 mW/Channel, Fully-Integrated, 8-Channel, 14- and 12-Bit, Ultrasound Analog Front-End With Passive CW Mixer

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AFE5808A
SLOS729D – OCTOBER 2011 – REVISED NOVEMBER 2015
PIN
NAME
NO.
AVDD_ADC
J6, J7, K8,
L3,
M1, M2
AVSS
C1, D1~D7,
E3~E7,
F3~F7,
G1~G7,
H3~H7,J3~J
5, K6
CLKM_ADC
L2
CLKP_ADC
L1
CLKM_16X
F9
CLKP_16X
F8
CLKM_1X
G9
CLKP_1X
G8
CM_BYP
B1
CW_IP_AMPINM
E2
CW_IP_AMPINP
E1
CW_IP_OUTM
F1
CW_IP_OUTP
F2
CW_QP_AMPINM
J2
CW_QP_AMPINP
J1
CW_QP_OUTM
CW_QP_OUTP
D1M~D8M
D1P~D8P
DCLKM
DCLKP
DNC
DVDD
DVSS
FCLKM
FCLKP
INM1…INM8
INP1...INP8
H1
H2
N8, P9~P7,
P3~P1, N2
N9, R9~R7,
R3~R1, N1
P6
R6
K7,
L5~L7,M5~
M8, N4, N6
N3, N7
N5, P5, R5
P4
R4
C9~C2
A9~A2
TYPE
Supply
—
I
I
I
I
I
I
Bias
O
O
O
O
O
O
O
O
O
O
O
O
—
Supply
—
O
O
I
I
Pin Functions (continued)
DESCRIPTION
1.8-V Analog power supply for ADC
Analog ground
Negative input of differential ADC clock. In the single-end clock mode, it can be tied to GND directly or through
a 0.1-µF capacitor.
Positive input of differential ADC clock. In the single-end clock mode, it can be tied to clock signal directly or
through a 0.1-µF capacitor.
Negative input of differential CW 16X clock. Tie to GND when the CMOS clock mode is enabled. In the 4X and
8X CW clock modes, this pin becomes the 4X or 8X CLKM input. In the 1X CW clock mode, this pin becomes
the in-phase 1X CLKM for the CW mixer. Can be floated if CW mode is not used.
Positive input of differential CW 16X clock. In 4X and 8X clock modes, this pin becomes the 4X or 8X CLKP
input. In the 1X CW clock mode, this pin becomes the in-phase 1X CLKP for the CW mixer. Can be floated if
CW mode is not used.
Negative input of differential CW 1X clock. Tie to GND when the CMOS clock mode is enabled (Refer to
Figure 88 for details). In the 1X clock mode, this pin is the quadrature-phase 1X CLKM for the CW mixer. Can
be floated if CW mode is not used.
Positive input of differential CW 1X clock. In the 1X clock mode, this pin is the quadrature-phase 1X CLKP for
the CW mixer. Can be floated if CW mode is not used.
Bias voltage and bypass to ground. ≥ 1 µF is recommended. To suppress the ultra low frequency noise, 10 µF
can be used.
Negative differential input of the In-phase summing amplifier. External LPF capacitor has to be connected
between CW_IP_AMPINM and CW_IP_OUTP. This pin becomes the CH7 PGA negative output when PGA
test mode is enabled. Can be floated if not used.
Positive differential input of the In-phase summing amplifier. External LPF capacitor has to be connected
between CW_IP_AMPINP and CW_IP_OUTM. This pin becomes the CH7 PGA positive output when PGA test
mode is enabled. Can be floated if not used.
Negative differential output for the In-phase summing amplifier. External LPF capacitor has to be connected
between CW_IP_AMPINP andCW_IP_OUTPM. Can be floated if not used.
Positive differential output for the In-phase summing amplifier. External LPF capacitor has to be connected
between CW_IP_AMPINM and CW_IP_OUTP. Can be floated if not used.
Negative differential input of the quadrature-phase summing amplifier. External LPF capacitor has to be
connected between CW_QP_AMPINM and CW_QP_OUTP. This pin becomes CH8 PGA negative output when
PGA test mode is enabled. Can be floated if not used.
Positive differential input of the quadrature-phase summing amplifier. External LPF capacitor has to be
connected between CW_QP_AMPINP and CW_QP_OUTM. This pin becomes CH8 PGA positive output when
PGA test mode is enabled. Can be floated if not used.
Negative differential output for the quadrature-phase summing amplifier. External LPF capacitor has to be
connected between CW_QP_AMPINP and CW_QP_OUTM. Can be floated if not used.
Positive differential output for the quadrature-phase summing amplifier. External LPF capacitor has to be
connected between CW_QP_AMPINM and CW_QP_OUTP. Can be floated if not used.
ADC CH1~8 LVDS negative outputs
ADC CH1~8 LVDS positive outputs
LVDS bit clock (7x) negative output
LVDS bit clock (7x) positive output
Do not connect. Must leave floated.
ADC digital and I/O power supply, 1.8 V
ADC digital ground
LVDS frame clock (1X) negative output
LVDS frame clock (1X) positive output
CH1~8 complimentary analog inputs. Bypass to ground with ≥ 0.015-µF capacitors. The HPF response of the
LNA depends on the capacitors.
CH1~8 analog inputs. AC couple to inputs with ≥ 0.1-µF capacitors.
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