ADS5424_14 Datasheet, PDF (7/29 Pages) Texas Instruments – 14 Bit, 105 MSPS Analog-to-Digital Converter

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PIN CONFIGURATION
ADS5424
PJY PACKAGE
(TOP VIEW)
SLWS157B − JANUARY 2005 − REVISED JANUARY 2010
DRV_DD
GND
VREF
GND
CLK
CLK
GND
AV_DD
AV_DD
GND
AIN
AIN
GND
52 51 50 49 48 47 46 45 44 43 42 41 40
1
39
2
38
3
37
4
36
5
35
6
34
7
GND
33
8
32
9
31
10
30
11
29
12
28
13
27
14 15 16 17 18 19 20 21 22 23 24 25 26
D3
D2
D1
D0 (LSB)
DMID
GND
DRV_DD
OVR
DNC
AV_DD
GND
AV_DD
GND
PIN ASSIGNMENTS
NAME
DRV_DD
GND
TERMINAL
NO.
1, 33, 43
DESCRIPTION
3.3 V power supply, digital output stage only
2, 4, 7, 10, 13, 15, Ground
17, 19, 21, 23, 25,
27, 29, 34, 42
VREF
3
2.4 V reference. Bypass to ground with a 0.1-µF microwave chip capacitor.
CLK
5
Clock input. Conversion initiated on rising edge.
CLK
6
Complement of CLK, differential input
AV_DD
8, 9, 14, 16, 18, 5 V analog power supply
22, 26, 28, 30
AIN
11
Analog input
AIN
12
Complement of AIN, differential analog input
C1
20
Internal voltage reference. Bypass to ground with a 0.1-µF chip capacitor.
C2
24
Internal voltage reference. Bypass to ground with a 0.1-µF chip capacitor.
DNC
31
Do not connect
OVR
32
Overrange bit. A logic level high indicates the analog input exceeds full scale.
DMID
D0 (LSB)
35
Output data voltage midpoint. Approximately equal to (DV_CC)/2
36
Digital output bit (least significant bit); two’s complement
D1−D5, D6−D12 37−41, 44−50 Digital output bits in two’s complement
D13 (MSB)
51
Digital output bit (most significant bit); two’s complement
DRY
52
Data ready output
7