ADC161S626 Datasheet, PDF (7/33 Pages) National Semiconductor (TI) – 16-Bit, 50 to 250 kSPS, Differential Input, MicroPower ADC

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ADC161S626
SNAS468D – SEPTEMBER 2008 – REVISED DECEMBER 2014
6.6 Timing Requirements
The following specifications apply for V_A = 4.5 V to 5.5 V, V_IO = 2.7 V to 5.5 V, V_REF = 2.5 V to 5.5 V, f_SCLK = 1Mz to 5MHz,
and C_L = 25 pF, unless otherwise noted. Maximum and minimum values apply for T_A = T_MIN to T_MAX; the typical values are
tested at T_A = 25°C.⁽¹⁾
MIN NOM MAX UNIT
t_CSS
CS Setup Time prior to an SCLK rising edge
t_CSH
CS Hold Time after an SCLK rising edge
t_DH
D_OUT Hold Time after an SCLK falling edge
t_DA
D_OUT Access Time after an SCLK falling edge
t_DIS
D_OUT Disable Time after the rising edge of CS⁽²⁾
t_CS
Minimum CS Pulse Width
t_EN
D_OUT Enable Time after the 2nd falling edge of SCLK
t_CH
SCLK High Time
t_CL
SCLK Low Time
t_r
D_OUT Rise Time
t_f
D_OUT Fall Time
8
3
ns
8
3
6
11
ns
18 41 ns
20 30 ns
20
ns
20 70 ns
20
ns
20
ns
7
ns
7
ns
(1) Typical values are at T_J = 25°C and represent most likely parametric norms. Test limits are specified to AOQL (Average Outgoing
Quality Level).
(2) t_DIS is the time for D_OUT to change 10% while being loaded by the Timing Test Circuit.
t_{CONV (Power-Up)}
t_ACQ
(Power-Down)
CS
SCLK
DOUT
t_CH
12
3
4 5 13 14 15 16 17
18
t_EN
t_CL
0 D15 D14
D5 D4 D3 D2 D1 D0
t_CS
12
t_DIS
0
Figure 1. ADC161S626 Single Conversion Timing Diagram
2 mA
I_OL
TO OUTPUT
PIN
CL
25 pF
2 mA
1.6V
I_OH
Figure 2. Timing Test Circuit
D_OUT
t_r
0.9 x V_IO
0.1 x V_IO
t_f
Figure 3. D_OUT Rise and Fall Times
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