ADC1175_14 Datasheet, PDF (7/29 Pages) Texas Instruments – 8-Bit, 20MHz, 60mW A/D Converter

ADC1175
www.ti.com
SNAS012H – JANUARY 2000 – REVISED APRIL 2013
CONVERTER ELECTRICAL CHARACTERISTICS (continued)
The following specifications apply for AV_DD = DV_DD = +5.0V_DC, OE = 0V, V_RT = +2.6V, V_RB = 0.6V, C_L = 20 pF, f_CLK = 20MHz
at 50% duty cycle. Boldface limits apply for T_A = T_MIN to T_MAX; all other limits T_A = 25°C ⁽¹⁾⁽²⁾
Symbol
Parameter
Conditions
Typical⁽³⁾ Limits⁽³⁾
Units
Power Supply Characteristics
IA_DD
ID_DD
IAV_DD +
IDV_DD
Analog Supply Current
Digital Supply Current
Total Operating Current
Power Consumption
CLK, OE Digital Input Characteristics
DV_DD = AV_DD =5.25V
DV_DD = AV_DD =5.25V
DV_DD AV_DD =5.25V, f_CLK = 20 MHz
DV_DD AV_DD =5.25V, f_CLK = 30 MHz
DV_DD = AV_DD =5.25V, CLK Low⁽⁴⁾
DV_DD = AV_DD =5.25V, f_CLK = 20 MHz
DV_DD = AV_DD =5.25V, f_CLK = 30 MHz
9.5
mA
2.5
mA
12
17
mA (max)
13
9.6
mA
60
85
mW (max)
65
mW
V_IH
Logical High Input Voltage
V_IL
Logical Low Input Voltage
I_IH
Logical High Input Current
I_IL
Logic Low Input Current
C_IN
Logic Input Capacitance
Digital Output Characteristics
DV_DD = AV_DD = +5.25V
DV_DD = AV_DD = +5.25V
V_IH = DV_DD = AV_DD = +5.25V
V_IL = 0V, DV_DD = AV_DD = +5.25V
3.0
V (min)
1.0
V (max)
5
µA
−5
µA
5
pF
I_OH
High Level Output Current
I_OL
Low Level Output Current
I_OZH,
I_OZL
Tri-State Leakage Current
AC Electrical Characteristics
DV_DD = 4.75V, V_OH = 2.4V
DV_DD = 4.75V, V_OL = 0.4V
DV_DD = 5.25V
OE = DV_DD, V_OL
= 0V or V_OH = DV_DD
−1.1
mA (max)
1.6
mA (min)
±20
µA
f_C1
Maximum Conversion Rate
f_C2
Minimum Conversion Rate
t_OD
Output Delay
CLK rise to data rising
CLK rise to data falling
30
20
MHz (min)
1
MHz
19.5
ns
16
ns
Pipeline Delay (Latency)
2.5
Clock Cycles
t_DS
Sampling (Aperture) Delay
t_AJ
Aperture Jitter
t_OH
Output Hold Time
t_EN
OE Low to Data Valid
t_DIS
OE High to High Z State
ENOB
Effective Number of Bits
SINAD Signal-to- Noise & Distortion
SNR
Signal-to- Noise Ratio
CLK low to acquisition of data
CLK high to data invalid
Loaded as in Figure 18
Loaded as in Figure 18
f_IN = 1.31 MHz, V_IN = FS - 2 LSB
f_IN = 4.43 MHz, V_IN = FS - 2 LSB
f_IN = 9.9 MHz, V_IN = FS - 2 LSB
f_IN = 4.43 MHz, f_CLK = 30 MHz
f_IN = 1.31 MHz, V_IN = FS - 2 LSB
f_IN = 4.43 MHz, V_IN = FS - 2 LSB
f_IN = 9.9 MHz, V_IN = FS - 2 LSB
f_IN = 4.43 MHz, f_CLK = 30 MHz
f_IN = 1.31 MHz, V_IN = FS - 2 LSB
f_IN = 4.43 MHz, V_IN = FS - 2 LSB
f_IN = 9.9 MHz, V_IN = FS - 2 LSB
f_IN = 4.43 MHz, f_CLK = 30 MHz
3
ns
30
ps rms
10
ns
11
ns
15
ns
7.5
7.3
7.0
Bits (min)
7.2
6.5
46.9
45.7
43
dB (min)
45.1
40.9
47.6
46
44
dB (min)
46.1
42.1
(4) At least two clock cycles must be presented to the ADC1175 after power up. See THE ADC1175 CLOCK for details.
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