ADC08L060_15 Datasheet, PDF (7/28 Pages) Texas Instruments – 10 MSPS to 60 MSPS, 0.65 mW/MSPS A/D Converter with Internal Sample-and-Hold

ADC08L060
www.ti.com
SNAS167G – MAY 2002 – REVISED MARCH 2013
Converter Electrical Characteristics (continued)
The following specifications apply for V_A = V_DR = +3.0V_DC, V_RT = +1.9V, V_RB = 0.3V, C_L = 10 pF, f_CLK = 60 MHz at 50% duty
cycle. Boldface limits apply for T_J = T_MIN to T_MAX: all other limits T_J = 25°C ^{(1)(2) (3)}
Symbol
Parameter
Conditions
Typical
(4)
Limits
(4)
Units
(Limits)
AC ELECTRICAL CHARACTERISTICS
f_C1
Maximum Conversion Rate
f_C2
Minimum Conversion Rate
t_CL
Minimum Clock Low Time
t_CH
Minimum Clock High Time
DC
Clock Duty Cycle
80
60
MHz (min)
10
MHz
0.62
ns (min)
0.62
ns (min)
5
%(min)
95
%(max)
t_OH
Output Hold Time
t_OD
Output Delay
CLK to Data Invalid
CLK to Data Transition
5.2
ns
5.0
ns (min)
7.1
9.4
ns (max)
Pipeline Delay (Latency)
5
Clock Cycles
t_AD
Sampling (Aperture) Delay
CLK Rise to Acquisition of Data
2.6
t_AJ
Aperture Jitter
2
ns
ps rms
Specification Definitions
APERTURE (SAMPLING) DELAY is that time required after the rise of the clock input for the sampling switch to
open. The Sample/Hold circuit effectively stops capturing the input signal and goes into the “hold” mode t_AD after
the clock goes high.
APERTURE JITTER is the variation in aperture delay from sample to sample. Aperture jitter shows up as input
noise.
CLOCK DUTY CYCLE is the ratio of the time that the clock wave form is at a logic high to the total time of one
clock period.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1
LSB. Measured at 60 MSPS with a ramp input.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise
and Distortion Ratio, or SINAD. ENOB is defined as (SINAD – 1.76) / 6.02 and says that the converter is
equivalent to a perfect ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental
drops 3 dB below its low frequency value for a full scale input.
FULL-SCALE ERROR is a measure of how far the last code transition is from the ideal 1½ LSB below V_RT and
is defined as:
V_max + 1.5 LSB – V_RT
(1)
where V_max is the voltage at which the transition to the maximum (full scale) code occurs.
INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from
zero scale (½ LSB below the first code transition) through positive full scale (½ LSB above the last code
transition). The deviation of any given code from this straight line is measured from the center of that code value.
The end point test method is used. Measured at 60 MSPS with a ramp input.
INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two
sinusoidal frequencies being applied to the ADC input at the same time. it is defined as the ratio of the power in
the second and third order intermodulation products to the power in one of the original frequencies. IMD is
usually expressed in dBFS.
LSB (LEAST SIGNIFICANT BIT) is the bit that has the smallest value or weight of all bits. This value is
(V_RT − V_RB) / 2ⁿ
(2)
where “n” is the ADC resolution, which is 8 in the case of the ADC08L060.
Copyright © 2002–2013, Texas Instruments Incorporated
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