TVP5146M2 Datasheet, PDF (69/107 Pages) Texas Instruments – NTSC/PAL/SECAM 4×10-Bit Digital Video Decoder With Macrovision™ Detection, YPbPr Inputs, 5-Line Comb Filter, and SCART Support

TVP5146M2
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SLES141H – JULY 2005 – REVISED FEBRUARY 2012
Table 2-72. Back-End AGC Control Register
Subaddress 6Ch
Default
08h
7
6
5
4
3
2
1
0
Reserved
1
Peak
Color
Sync
This register disables the back-end AGC when the front-end AGC uses specific amplitude references (sync-height, color burst, or
composite peak) to decrement the front-end gain. For example, writing 0x09 to this register disables the back−end AGC when the front-end
AGC uses the sync-height to decrement the front-end gain.
Peak:
Disables back-end AGC when the front-end AGC uses the composite peak as an amplitude reference.
0 = Disabled (default)
1 = Enabled
Color:
Disables back-end AGC when the front-end AGC uses the color burst as an amplitude reference.
0 = Disabled (default)
1 = Enabled
Sync:
Disables back-end AGC when the front-end AGC uses the sync height as an amplitude reference.
0 = Disabled (default)
1 = Enabled
Table 2-73. AGC Decrement Speed Register
Subaddress 6Fh
Default
04h
7
6
5
4
3
Reserved
AGC decrement speed:
Adjusts gain decrement speed. Only used for composite/luma peaks.
111 = 7 (slowest)
110 = 6 (default)
⋮
000 = 0 (fastest)
2
1
0
AGC decrement speed [2:0]
Table 2-74. ROM Version Register
Subaddress 70h
Read only
7
6
5
4
3
2
1
0
ROM version [7:0]
ROM Version [7:0]:
ROM revision number
Table 2-75. RAM Version MSB Register
Subaddress 71h
Read only
7
6
5
4
3
2
1
0
RAM version MSB [7:0]
RAM version MSB [7:0]:
This register identifies the MSB of the RAM code revision number.
Copyright © 2005–2012, Texas Instruments Incorporated
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Functional Description
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