TMS570LS20216_14 Datasheet, PDF (69/107 Pages) Texas Instruments – TMS570LS Series 16/32-BIT RISC Flash Microcontroller

TMS570LS20216, TMS570LS20206, TMS570LS10216
TMS570LS10206, TMS570LS10116, TMS570LS10106
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SPNS141F – AUGUST 2010 – REVISED JULY 2011
7.1.5 Switching Characteristics Over Recommended Operating Conditions For Clocks
Table 7-4. Switching Characteristics Over Recommended Operating Conditions For Clocks
Parameter
Test Conditions
MIN
MAX
Unit
f_(HCLK)
HCLK - System clock frequency (337 BGA
packages)
Pipeline mode enabled
Pipeline mode disabled
160
MHz
36
MHz
f_(HCLK)
HCLK - System clock frequency (144pin QFP
package)
Pipeline mode enabled
Pipeline mode disabled
140
MHz
36
MHz
f_(GCLK)
GCLK - CPU clock frequency (ratio GCLK :
HCLK = 1:1)
f_(HCLK)
MHz
f_(RCLK)
f_(RTICLK) ⁽¹⁾
f_(VCLK)
f_(VCLK2)
f_(AVCLK1)
RCLK - Frequency out of PLL macro into
R-divider
RTICLK - clock frequency
VCLK - Primary peripheral clock frequency
VCLK2 - Secondary peripheral clock frequency
AVCLK1 - Primary asynchronous peripheral clock
frequency
160
f_(VCLK)
f_(VCLK2)
100
f_(VCLK)
MHz
MHz
MHz
MHz
MHz
f_(AVCLK2)
f_(ECLK) ⁽²⁾
AVCLK2 - Secondary asynchronous peripheral
clock frequency
ECLK - External clock output frequency for ECP
Module
f_(VCLK)
80
MHz
MHz
f_(PROG/ERASE)
System clock frequency - Flash
programming/erase
f_(HCLK)
MHz
(1) If the RTIx clock source is chosen to be anything other than the default VCLK, then the RTI clock needs to be at least three times slower
than the VCLK.
(2) (ECLK) = f(VCLK) / N, where N = {1 to 65536}. N is the ECP prescale value defined by the ECPCNTL.[15:0] register bits in the System
module. Pipeline mode enabled or disabled is determined by the FRDCNTL[2:0].
7.1.5.1 Timing - Wait States
RAM
Address Waitstates
Data Waitstates
Flash
Address Waitstates
Data Waitstates
0
0MHz
0
0MHz
0MHz
0
100MHz
0
0MHz
36MHz
1
2
72MHz
108MHz
Figure 7-3. Wait States
1
3
f(HCLK)
f(HCLK)
f(HCLK)
f(HCLK)
NOTE
If FMzPLL frequency modulation is enabled, special care must be taken to ensure that the
maximum system clock frequency f(HCLK) and peripheral clock frequency f(VCLK) are not
exceeded. The speed of the device clocks may need be derated to accommodate the
modulation depth when FMzPLL frequency modulation is enabled.
Copyright © 2010–2011, Texas Instruments Incorporated
Peripheral and Electrical Specifications
69
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