ADC32RF45 Datasheet, PDF (69/108 Pages) Texas Instruments – Analog-to-Digital Converter

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8.5.7.3 Register 003h (address = 003h), JESD Digital Page
ADC32RF45
SBAS747B – MAY 2016 – REVISED JULY 2016
Figure 89. Register 003h
7
6
5
4
LINK LAYER TESTMODE
LINK LAY RPAT
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
3
LMFC MASK RES
R/W-0h
2
JESD MODE1
R/W-1h
1
JESD MODE2
R/W-0h
0
RAMP 12BIT
R/W-0h
Table 50. Register 003h Field Descriptions
Bit Field
7-5 LINK LAYER TESTMODE
4
LINK LAY RPAT
3
LMFC MASK RES
2
JESD MODE1
1
JESD MODE2
0
RAMP 12BIT
Type
R/W
Reset
0h
R/W
0h
R/W
0h
R/W
1h
R/W
0h
R/W
0h
Description
These bits generate a pattern according to section 5.3.3.8.2 of
the JESD204B document.
000 = Normal ADC data
001 = D21.5 (high-frequency jitter pattern)
010 = K28.5 (mixed-frequency jitter pattern)
011 = Repeat initial lane alignment (generates a K28.5 character
and repeats lane alignment sequences continuously)
100 = 12-octet RPAT jitter pattern
This bit changes the running disparity in a modified RPAT
pattern test mode (only when link layer test mode = 100).
0 = Normal operation
1 = Changes disparity
TBD
These bits select the configuration register to configure the
correct LMFS frame assemblies for different decimation settings;
see JESD frame assembly tables in the JESD204B Frame
Assembly section
These bits select the configuration register to configure the
correct LMFS frame assemblies for different decimation settings;
see JESD frame assembly tables in the JESD204B Frame
Assembly section
This bit enables the RAMP test pattern for 12-bit mode only
(LMFS = 82820).
0 = Normal data output
1 = Digital output is the RAMP pattern
8.5.7.4 Register 004h (address = 004h), JESD Digital Page
Figure 90. Register 004h
7
6
5
4
0
0
0
0
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
3
0
W-0h
2
0
W-0h
1
0
REL ILA SEQ
R/W-0h
Bit Field
7-2 0
1-0 REL ILA SEQ
Table 51. Register 004h Field Descriptions
Type
W
R/W
Reset
0h
0h
Description
Must write 0
These bits delay the generation of the lane alignment sequence
by 0, 1, 2, or 3 multiframes after the code group synchronization.
00 = 0 multiframe delays
01 = 1 multiframe delay
10 = 2 multiframe delays
11 = 3 multiframe delays
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