LM3S3N26 Datasheet, PDF (685/877 Pages) Texas Instruments – Stellaris® LM3S3N26 Microcontroller

Stellaris^® LM3S3N26 Microcontroller
Figure 15-2. I²C Bus Configuration
SCL
SDA
RPUP RPUP
I2C Bus
I2CSCL I2CSDA
Stellaris®
SCL
SDA
3rd Party Device
with I2C Interface
SCL
SDA
3rd Party Device
with I2C Interface
15.3.1
I²C Bus Functional Overview
The I²C bus uses only two signals: SDA and SCL, named I2CSDA and I2CSCL on Stellaris
microcontrollers. SDA is the bi-directional serial data line and SCL is the bi-directional serial clock
line. The bus is considered idle when both lines are High.
Every transaction on the I²C bus is nine bits long, consisting of eight data bits and a single
acknowledge bit. The number of bytes per transfer (defined as the time between a valid START
and STOP condition, described in “START and STOP Conditions” on page 685) is unrestricted, but
each byte has to be followed by an acknowledge bit, and data must be transferred MSB first. When
a receiver cannot receive another complete byte, it can hold the clock line SCL Low and force the
transmitter into a wait state. The data transfer continues when the receiver releases the clock SCL.
15.3.1.1
START and STOP Conditions
The protocol of the I²C bus defines two states to begin and end a transaction: START and STOP.
A High-to-Low transition on the SDA line while the SCL is High is defined as a START condition,
and a Low-to-High transition on the SDA line while SCL is High is defined as a STOP condition.
The bus is considered busy after a START condition and free after a STOP condition. See Figure
15-3.
Figure 15-3. START and STOP Conditions
SDA
SCL
START
condition
STOP
condition
SDA
SCL
The STOP bit determines if the cycle stops at the end of the data cycle or continues on to a repeated
START condition. To generate a single transmit cycle, the I²C Master Slave Address (I2CMSA)
register is written with the desired address, the R/S bit is cleared, and the Control register is written
with ACK=X (0 or 1), STOP=1, START=1, and RUN=1 to perform the operation and stop. When the
operation is completed (or aborted due an error), the interrupt pin becomes active and the data may
be read from the I²C Master Data (I2CMDR) register. When the I²C module operates in Master
receiver mode, the ACK bit is normally set causing the I²C bus controller to transmit an acknowledge
automatically after each byte. This bit must be cleared when the I²C bus controller requires no further
data to be transmitted from the slave transmitter.
When operating in slave mode, two bits in the I²C Slave Raw Interrupt Status (I2CSRIS) register
indicate detection of start and stop conditions on the bus; while two bits in the I²C Slave Masked
January 21, 2012
685
Texas Instruments-Production Data