LM3S5G36 Datasheet, PDF (683/1068 Pages) Texas Instruments – Stellaris® LM3S5G36 Microcontroller

Stellaris^® LM3S5G36 Microcontroller
Assuming the system clock is 20 MHz, the bit rate calculation would be:
SSIClk = SysClk / (CPSDVSR * (1 + SCR))
1x106 = 20x106 / (CPSDVSR * (1 + SCR))
In this case, if CPSDVSR=0x2, SCR must be 0x9.
The configuration sequence would be as follows:
1. Ensure that the SSE bit in the SSICR1 register is clear.
2. Write the SSICR1 register with a value of 0x0000.0000.
3. Write the SSICPSR register with a value of 0x0000.0002.
4. Write the SSICR0 register with a value of 0x0000.09C7.
5. The SSI is then enabled by setting the SSE bit in the SSICR1 register.
14.5
Register Map
Table 14-2 on page 683 lists the SSI registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that SSI module’s base address:
■ SSI0: 0x4000.8000
■ SSI1: 0x4000.9000
Note that the SSI module clock must be enabled before the registers can be programmed (see
page 258). There must be a delay of 3 system clocks after the SSI module clock is enabled before
any SSI module registers are accessed.
Note: The SSI must be disabled (see the SSE bit in the SSICR1 register) before any of the control
registers are reprogrammed.
Table 14-2. SSI Register Map
Offset Name
Type
0x000 SSICR0
0x004 SSICR1
0x008 SSIDR
0x00C SSISR
0x010 SSICPSR
0x014 SSIIM
0x018 SSIRIS
0x01C SSIMIS
0x020 SSIICR
0x024 SSIDMACTL
0xFD0 SSIPeriphID4
R/W
R/W
R/W
RO
R/W
R/W
RO
RO
W1C
R/W
RO
Reset
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0003
0x0000.0000
0x0000.0000
0x0000.0008
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
Description
SSI Control 0
SSI Control 1
SSI Data
SSI Status
SSI Clock Prescale
SSI Interrupt Mask
SSI Raw Interrupt Status
SSI Masked Interrupt Status
SSI Interrupt Clear
SSI DMA Control
SSI Peripheral Identification 4
See
page
685
687
689
690
692
693
694
696
698
699
700
January 23, 2012
683
Texas Instruments-Production Data