TAS5508B_17 Datasheet, PDF (68/104 Pages) Texas Instruments – 8-Channel Digital Audio PWM Processor

TAS5508B
8-Channel Digital Audio PWM Processor
SLES162C – DECEMBER 2005 – REVISED JULY 2009
www.ti.com
I²C
SUBADDRESS
0x4F
0x50
0x51–0x88
0x89–0x90
0x91
0x92
0x93
0x94
0x95
0x96
0x97
0x98
0x99
0x9A
0x9B
0x9C
0x9D
0x9E
0x9F
0xA0
0xA1
TOTAL
BYTES
4
4
20/reg.
8
4
8
4
8
20
4
4
8
16
12
16
16
8
16
12
16
16
REGISTER FIELDS
DESCRIPTION OF CONTENTS
Ch8_bp_bq2
Ch8_bq2
Biquad filter register
Bass and treble bypass
register, Ch1–Ch8
Loudness Log2 LG
Loudness Log2 LO
Loudness G
Loudness O
Loudness biquad
DRC1 control Ch1–Ch7
DRC2 control register, Ch8
Ch1–Ch7, DRC1 energy
Ch1–Ch7,
DRC1 (1 – energy)
Ch1–Ch7 DRC1 threshold
T1
Ch1–Ch7 DRC1 threshold
T2
Ch1–Ch7 , DRC1 slope k0
Ch1–Ch7, DRC1 slope k1
Ch1–Ch7 DRC1 slope k2
Ch1–Ch7 DRC1 offset 1
Ch1–Ch7 DRC1 offset 2
Ch1–Ch7 DRC1 attack
Ch1–Ch7 DRC1 (1 – attack)
Ch1–Ch7 DRC1 decay
Ch1–Ch7 DRC1 (1 – decay)
Ch8 DRC2 energy
Ch8 DRC2 (1 – energy)
Ch8 DRC2 threshold T1
Ch8 DRC2 threshold T2
Ch8 DRC2 slope k0
Ch8 DRC2 slope k1
Ch8 DRC2 slope k2
Ch8 DRC2 offset 1
Ch8 DRC2 offset 2
Ch8 DRC2 attack
Ch8 DRC2 (1 – attack)
Ch8 DRC2 decay
Ch8 DRC2 (1 – decay)
Bypass Ch8 biquad 2 coefficient
Ch8 biquad 2 coefficient
Ch1–Ch8 biquad filter coefficients
Bypass bass and treble for Ch1–Ch8
Loudness Log2 LG
Loudness Log2 LO
Loudness G
Loudness O
Loudness biquad coefficient b0
Loudness biquad coefficient b1
Loudness biquad coefficient b2
Loudness biquad coefficient a0
Loudness biquad coefficient a1
DRC1 control Ch1–Ch7
DRC2 control Ch8
DRC1 energy
DRC1 (1 – energy)
DRC1 threshold (T1) – upper 2 bytes
DRC1 threshold (T1) – lower 4 bytes
DRC1 threshold (T2) – upper 2 bytes
DRC1 threshold (T2) – lower 4 bytes
DRC1 slope (k0)
DRC1 slope (k1)
DRC1 slope (k2)
DRC1 offset 1 (O1) – upper 2 bytes
DRC1 offset 1 (O1) – lower 4 bytes
DRC1 offset 2 (O2) – upper 2 bytes
DRC1 offset 2 (O2) – lower 4 bytes
DRC1 attack
DRC1 (1 – attack)
DRC1 decay
DRC1 (1 – decay)
DRC2 energy
DRC2 (1 – energy)
DRC2 threshold (T1) – upper 2 bytes
DRC2 threshold (T1) – lower 4 bytes
DRC2 threshold (T2) – upper 2 bytes
DRC2 threshold (T2) – lower 4 bytes
DRC2 slope (k0)
DRC2 slope (k1)
DRC2 slope (k2)
DRC2 offset (O1) – upper 2 bytes
DRC2 offset (O1) – lower 4 bytes
DRC2 offset (O2) – upper 2 bytes
DRC2 offset (O2) – lower 4 bytes
DRC 2 attack
DRC2 (1 – attack)
DRC2 decay
DRC2 (1 – decay)
DEFAULT STATE
0.0
1.0
All biquads = All pass for all channels
Bass and treble bypassed for all channels
0.5
0.0
0.0
0.0
0x00, 0x00, 0xD5, 0x13
0x00, 0x00, 0x00, 0x00
0x0F, 0xFF, 0x2A, 0xED
0x00, 0xFE, 0x50, 0x45
0x0F, 0x81, 0xAA, 0x27
DRC1 disabled in Ch1–Ch7
DRC2 disabled in Ch8
0.0041579
0.9958421
0x00, 0x00, 0x00, 0x00
0x0B, 0x20, 0xE2, 0xB2
0x00, 0x00, 0x00, 0x00
0x06, 0xF9, 0xDE, 0x58
0x0F, 0xC0, 0x00, 0x00
0x0F, 0xC0, 0x00, 0x00
0x0F, 0x90, 0x00, 0x00
0x00, 0x00, 0xFF, 0xFF
0xFF, 0x82, 0x30, 0x98
0x00, 0x00, 0x00, 0x00
0x01, 0x95, 0xB2, 0xC0
0x00, 0x00, 0x88, 0x3F
0x00, 0x7F, 0x77, 0xC0
0x00, 0x00, 0x00, 0xAE
0x00, 0x7F, 0xFF, 0x51
0x00, 0x00, 0x88, 0x3F
0x00, 0x7F, 0x77, 0xC0
0x00, 0x00, 0x00, 0x00
0x0B, 0x20, 0xE2, 0xB2
0x00, 0x00, 0x00, 0x00
0x06, 0xF9, 0xDE, 0x58
0x00, 0x40, 0x00, 0x00
0x0F, 0xC0, 0x00, 0x00
0x0F, 0x90, 0x00, 0x00
0x00, 0x00, 0xFF, 0xFF
0xFF, 0x82, 0x30, 0x98
0x00, 0x00, 0x00, 0x00
0x01, 0x95, 0xB2, 0xC0
0x00, 0x00, 0x88, 0x3F
0x00, 0x7F, 0x77, 0xC0
0x00, 0x00, 0x00, 0xAE
0x00, 0x7F, 0xFF, 0x51
68
Serial-Control I²C Register Summary
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