PGA400-Q1_16 Datasheet, PDF (68/119 Pages) Texas Instruments – PGA400-Q1 Pressure-Sensor Signal Conditioner

PGA400-Q1
SLDS186A – MARCH 2012 – REVISED JULY 2016
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7.10.2.5 Timer/Counter Control (TCON)
Two 16-bit timer/counters are provided. TCON and TMOD are used to set the mode of operation and to control
the running and interrupt generation of the timer/counters. The timer/counter values are stored in two pairs of 8-
bit registers (TL0, TH0, and TL1, TH1).
Timer/Counter Register (TCON)
SFR:
0x88
TCON
BIT 7
BIT 6
BIT 5
TF1
TR1
TF0
Access
r/w
r/w
r/w
At Reset
0
0
0
Bit Addressable
BIT 4
TR0
r/w
0
BIT 3
IE1
r/w
0
BIT 2
IT1
r/w
0
BIT 1
IE0
r/w
0
BIT 0
IT0
r/w
0
The bit definitions for this register are as follows.
Timer1
BIT7: TF1
Timer1
BIT6: TR1
Timer0
BIT5: TF0
Timer0
BIT4: TR0
External Interrupt1
BIT3: IE1
External Interrupt1
BIT2: IT1
External Interrupt0
BIT1: IE0
External Interrupt0
BIT0: IT0
Timer 1 overflow flag. Set by hardware when Timer/Counter 1 overflows. Cleared by
hardware when the processor calls the interrupt service routine.
Timer 1 run control. If “1”, timer runs; if “0”, timer is halted.
Timer 0 overflow flag. Set by hardware when Timer/Counter 0 overflows. Cleared by
hardware when the processor calls the interrupt service routine.
Timer 0 run control. If “1”, timer runs; if “0”, timer is halted.
External Interrupt 1 edge flag. Set by hardware when an External Interrupt 1 edge is
detected.
External Interrupt 1 control bit. If “1”, External Interrupt 1 is “edge-triggered”; if “0”,
External Interrupt 1 is “level triggered”
External Interrupt 0 edge flag. Set by hardware when an External Interrupt 0 edge is
detected.
External Interrupt 1 control bit. If “1”, External Interrupt 1 is “edge-triggered”; if “0”,
External Interrupt 1 is “level triggered”
7.10.2.6 Timer/Counter Mode (TMOD)
Timer/Counter Mode (TMOD)
SFR:
0x89
TCON
BIT 7
BIT 6
BIT 5
GATE1
CNT1
M1 (1)
Access
r/w
r/w
r/w
At Reset
0
0
0
Not Bit Addressable
BIT 4
M0 (1)
r/w
0
BIT 3
GATE0
r/w
0
BIT 2
CNT0
r/w
0
BIT 1
M1 (0)
r/w
0
BIT 0
M0 (0)
r/w
0
The bit definitions for this register are as follows.
Timer1
BIT7: GATE1
Timer 1 gate flag. When TCON.6 is set and GATE1= 1, Timer/Counter 1 will only run if NINT1 pin is
1 (hardware control). When GATE1= 0, Timer/Counter 1 will only run if TCON.6 = 1 (software
control).
Timer1
BIT6: CNT1 Timer/Counter 1 selector. If 0, input is from internal system clock; if “1”, input is from T1 pin.
Timer1
BIT5: M1(1) Timer 1 Mode control bit M1.
Timer1
BIT4: M0(1) Timer 1 Mode control bit M0.
Timer0
BIT3: GATE0
Timer 0 gate flag. When TCON.4 is set and GATE0= 1, Timer/Counter 0 will only run if NINT0 pin is
1 (hardware control). When GATE0 = 0, Timer/Counter 0 will only run if TCON.4 = 1 (software
control).
Timer0
BIT2: CNT0 Timer/Counter 0 selector. If 0, input is from internal system clock; if “1”, input is from T0 pin.
Timer0
BIT1: M1(0) Timer 0 Mode control bit M1.
Timer0
BIT0: M0(0) Timer 0 Mode control bit M0.
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