ADS5294_15 Datasheet, PDF (67/81 Pages) Texas Instruments – Octal-Channel 14-Bit 80-MSPS High-SNR and Low-Power ADC

www.ti.com
ADS5294
SLAS776D – NOVEMBER 2011 – REVISED SEPTEMBER 2015
Typical Application (continued)
The ADS5294 clock input can be driven by either a differential clocks (sine wave, LVPECL, or LVDS) or a
singled clock(LVCMOS). In the single-ended case, TI recommends that the use of low jitter square signals
(LVCMOS levels, 1.8-V amplitude). See TI document SLYT075 for further details on the theory.
The jitter cleaner CDCM7005 SCAS793, CDCE72010 SLAS490, LMK04803 SNAS489 is suitable to generate the
ADC clock of the ADS5294 and ensure the performance for the14-bit ADC with >75-dBFS SNR. Please note that
the location of LVDS Rterm depends on the LVDS clock driver. Some clock devices require the Rterm at the left
side of AC coupling capacitors.
SINGLE-ENDED CLOCK CONNECTIONS
CMOS
CLOCK IN
CLKP
VCM
CLKM
ADS529x
Figure 64. Single-Ended Clock Drive Circuit
DIFFERENTIAL CLOCK CONNECTIONS
0.1 mF
Differential sine-
wave clock input
CLKP
0.1 mF
CLKM
ADS529x
Differential
LVPECL
clock input
0.1 mF
R_term
CLKP
0.1 mF
R_term
CLKM
ADS529x
Differential
LVDS
clock input
0.1 mF
R_term
CLKP
0.1 mF
CLKM
ADS529x
Figure 65. Differential Clock Drive Circuit
Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: ADS5294
Submit Documentation Feedback
67