TVP5154A Datasheet, PDF (66/92 Pages) Texas Instruments – 4-Channel Low-Power PAL/NTSC/SECAM Video Decoder With Independent Scalers and Fast Lock

TVP5154A
SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010
7.2.67 Interrupt Enable Register A
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Address
C1h
Default
00h
7
6
5
Reserved Lock interrupt Cycle complete
enable
interrupt enable
Lock interrupt enable:
0 = Disabled (default)
1 = Enabled
Cycle complete interrupt enable:
0 = Disabled (default)
1 = Enabled
Bus error interrupt enable:
0 = Disabled (default)
1 = Enabled
FIFO threshold interrupt enable:
0 = Disabled (default)
1 = Enabled
Line interrupt enable:
0 = Disabled (default)
1 = Enabled
Data interrupt enable:
0 = Disabled (default)
1 = Enabled
4
Bus error
interrupt enable
3
Reserved
2
FIFO threshold
interrupt enable
1
Line interrupt
enable
0
Data interrupt
enable
The interrupt enable register A is used by the host processor to mask unnecessary interrupt sources. Bits
loaded with a 1 allow the corresponding interrupt condition to generate an interrupt on the external pin.
Conversely, bits loaded with a 0 mask the corresponding interrupt condition from generating an interrupt
on the external pin. This register only affects the interrupt on the external terminal, it does not affect the
bits in interrupt status register A. A given condition can set the appropriate bit in the status register and not
cause an interrupt on the external terminal. To determine if this device is driving the interrupt terminal
either perform a logical AND of interrupt status register A with interrupt enable register A, or check the
state of the interrupt A bit in the interrupt configuration register at address C2h.
66
Internal Control Registers
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