AFE5808_14 Datasheet, PDF (65/76 Pages) Texas Instruments – Fully Integrated, 8-Channel Ultrasound Analog Front End With Passive CW Mixer, 0.75 nV/rtHz, 14/12-Bit, 65 MSPS, 153 mW/CH

AFE5808
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POWER MANAGEMENT
SLOS688D – SEPTEMBER 2010 – REVISED JANUARY 2014
Power/Performance Optimization
The AFE5808 has options to adjust power consumption and meet different noise performances. This feature
would be useful for portable systems operated by batteries when low power is more desired. See the
characteristics information listed in the table of electrical characteristics as well as the typical characteristic plots.
Power Management Priority
Power management plays a critical role to extend battery life and ensure long operation time. The AFE5808 has
fast and flexible power down/up control which can maximize battery life. The AFE5808 can be powered-down or
powered-up through external pins or internal registers. The following table indicates the affected circuit blocks
and priorities when the power management is invoked. The higher priority controls can overwrite the lower
priority ones. In the device, all the power down controls are logically ORed to generate final power down for
different blocks. Thus, the higher priority controls can cover the lower priority controls
Pin
Pin
Register
Register
Pin
Register
Register
Register
Register
Table 17. Power Management Priority
Name
PDN_GLOBAL
PDN_VCA
VCA_PARTIAL_PDN
VCA_COMPLETE_PDN
PDN_ADC
ADC_PARTIAL_PDN
ADC_COMPLETE_PDN
PDN_VCAT_PGA
PDN_LNA
Blocks
All
LNA + VCAT+ PGA
LNA + VCAT+ PGA
LNA + VCAT+ PGA
ADC
ADC
ADC
VCAT + PGA
LNA
Priority
High
Medium
Low
Medium
Medium
Low
Medium
Lowest
Lowest
Partial Power-Up and Power-Down Mode
The partial power-up and power-down mode is also called as fast power-up and power-down mode. In this mode,
most amplifiers in the signal path are powered down, while the internal reference circuits remain active as well as
the LVDS clock circuit, that is the LVDS circuit still generates its frame and bit clocks.
The partial power down function allows the AFE5808 to be wake up from a low-power state quickly. This
configuration ensures that the external capacitors are discharged slowly; thus a minimum wake-up time is
needed as long as the charges on those capacitors are restored. The VCA wake-up response is typically about 2
μs or 1% of the power down duration whichever is larger. The longest wake-up time depends on the capacitors
connected at INP and INM, as the wake-up time is the time required to recharge the caps to the desired
operating voltages. For 0.1 μF at INP and 15 nF at INM can give a wake-up time of 2.5 ms. For larger capacitors
this time will be longer. The ADC wake-up time is about 1 μs. Thus the AFE5808 wake-up time is more
dependent on the VCA wake-up time. This also assumes that the ADC clock has been running for at least 50 µs
before normal operating mode resumes. The power-down time is instantaneous, less than 1.0 µs.
This fast wake-up response is desired for portable ultrasound applications in which the power saving is critical.
The pulse repetition frequency of a ultrasound system could vary from 50 kHz to 500 Hz, while the imaging depth
(that is the active period for a receive path) varies from 10 μs to hundreds of µs. The power saving can be pretty
significant when a system’s PRF is low. In some cases, only the VCA would be powered down while the ADC
keeps running normally to ensure minimal impact to FPGAs.
In the partial power-down mode, the AFE5808 typically dissipates only 26 mW/ch, representing an 80% power
reduction compared to the normal operating mode. This mode can be set using either pins (PDN_VCA and
PDN_ADC) or register bits (VCA_PARTIAL_PDN and ADC_PARTIAL_PDN).
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