LM3S6537 Datasheet, PDF (646/732 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Signal Tables
19 Signal Tables
19.1
Important: All multiplexed pins are GPIOs by default, with the exception of the five JTAG pins (PB7
and PC[3:0]) which default to the JTAG functionality.
The following tables list the signals available for each pin. Functionality is enabled by software with
the GPIOAFSEL register. All digital inputs are Schmitt triggered.
■ Signals by Pin Number
■ Signals by Signal Name
■ Signals by Function, Except for GPIO
■ GPIO Pins and Alternate Functions
■ Connections for Unused Signals
100-Pin LQFP Package Pin Tables
19.1.1 Signals by Pin Number
Table 19-1. Signals by Pin Number
Pin Number
1
2
Pin Name
ADC0
ADC1
VDDA
Pin Type
I
I
-
3
GNDA
-
4
5
ADC2
I
6
ADC3
I
LDO
-
7
8
VDD
-
9
GND
-
PD0
I/O
10
PWM0
O
PD1
I/O
11
PWM1
O
PD2
I/O
12
U1Rx
I
Buffer Type^a Description
Analog Analog-to-digital converter input 0.
Analog Analog-to-digital converter input 1.
Power
The positive supply for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from VDD to minimize
the electrical noise contained on VDD from affecting the analog
functions. VDDA pins must be supplied with a voltage that meets
the specification in “Recommended DC Operating
Conditions” on page 676, regardless of system implementation.
Power
The ground reference for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from GND to minimize
the electrical noise contained on VDD from affecting the analog
functions.
Analog Analog-to-digital converter input 2.
Analog Analog-to-digital converter input 3.
Power
Low drop-out regulator output voltage. This pin requires an external
capacitor between the pin and GND of 1 µF or greater. The LDO
pin must also be connected to the VDD25 pins at the board level
in addition to the decoupling capacitor(s).
Power Positive supply for I/O and some logic.
Power Ground reference for logic and I/O pins.
TTL
GPIO port D bit 0.
TTL
PWM 0. This signal is controlled by PWM Generator 0.
TTL
GPIO port D bit 1.
TTL
PWM 1. This signal is controlled by PWM Generator 0.
TTL
GPIO port D bit 2.
TTL
UART module 1 receive. When in IrDA mode, this signal has IrDA
modulation.
646
June 18, 2012
Texas Instruments-Production Data