TM4C123BE6PM Datasheet, PDF (644/1276 Pages) Texas Instruments – Tiva TM4C123BE6PM Microcontroller

General-Purpose Input/Outputs (GPIOs)
3. Configure the GPIOAFSEL register to program each bit as a GPIO or alternate pin. If an alternate
pin is chosen for a bit, then the PMCx field must be programmed in the GPIOPCTL register for
the specific peripheral required. There are also two registers, GPIOADCCTL and GPIODMACTL,
which can be used to program a GPIO pin as a ADC or μDMA trigger, respectively.
4. Set the drive strength for each of the pins through the GPIODR2R, GPIODR4R, and GPIODR8R
registers.
5. Program each pad in the port to have either pull-up, pull-down, or open drain functionality through
the GPIOPUR, GPIOPDR, GPIOODR register. Slew rate may also be programmed, if needed,
through the GPIOSLR register.
6. To enable GPIO pins as digital I/Os, set the appropriate DEN bit in the GPIODEN register. To
enable GPIO pins to their analog function (if available), set the GPIOAMSEL bit in the
GPIOAMSEL register.
7. Program the GPIOIS, GPIOIBE, GPIOEV, and GPIOIM registers to configure the type, event,
and mask of the interrupts for each port.
Note: To prevent false interrupts, the following steps should be taken when re-configuring
GPIO edge and interrupt sense registers:
a. Mask the corresponding port by clearing the IME field in the GPIOIM register.
b. Configure the IS field in the GPIOIS register and the IBE field in the GPIOIBE
register.
c. Clear the GPIORIS register.
d. Unmask the port by setting the IME field in the GPIOIM register.
8. Optionally, software can lock the configurations of the NMI and JTAG/SWD pins on the GPIO
port pins, by setting the LOCK bits in the GPIOLOCK register.
When the internal POR signal is asserted and until otherwise configured, all GPIO pins are configured
to be undriven (tristate): GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, and GPIOPUR=0, except for
the pins shown in Table 10-1 on page 637. Table 10-3 on page 644 shows all possible configurations
of the GPIO pads and the control register settings required to achieve them. Table 10-4 on page 645
shows how a rising edge interrupt is configured for pin 2 of a GPIO port.
Table 10-3. GPIO Pad Configuration Examples
Configuration
GPIO Register Bit Value^a
AFSEL DIR
ODR
DEN
Digital Input (GPIO)
0
0
0
1
Digital Output (GPIO)
0
1
0
1
Open Drain Output
0
1
1
1
(GPIO)
Open Drain
1
X
1
1
Input/Output (I2CSDA)
Digital Input/Output
1
X
0
1
(I2CSCL)
Digital Input (Timer
1
X
0
1
CCP)
PUR
?
?
X
X
X
?
PDR
?
?
X
X
X
?
DR2R
X
?
?
?
?
X
DR4R
X
?
?
?
?
X
DR8R
X
?
?
?
?
X
SLR
X
?
?
?
?
X
644
June 12, 2014
Texas Instruments-Production Data