AFE5807ZCF Datasheet, PDF (64/74 Pages) Texas Instruments – Fully Integrated, 8-Channel Ultrasound Analog Front End

AFE5807
SLOS703C – SEPTEMBER 2010 – REVISED MAY 2013
FPGA Clock/
Noisy Clock
n×16×CW Freq
LMK048X
CDCE72010
CDCM7005
16X CW
CLK
CDCLVP1208
LMK0030X
LMK01000
8 Synchronized
16 X CW CLKs
1X CW
CLK
CDCLVP1208
LMK0030X
LMK01000
8 Synchronized
1X CW CLKs
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Figure 90. CW Clock Distribution
B0436-01
CW Supporting Circuits
As a general practice in CW circuit design, in-phase and quadrature channels should be strictly symmetrical by
using well matched layout and high accuracy components.
In systems, additional high-pass wall filters (20Hz to 500Hz) and low-pass audio filters (10KHz to 100KHz) with
multiple poles are usually needed. Since CW Doppler signal ranges from 20Hz to 20KHz, noise under this range
is critical. Consequently low noise audio operational amplifiers are suitable to build these active filters for CW
post-processing, e.g. OPA1632 or OPA2211. More filter design techniques can be found from www.ti.com, e.g.
TI’s active filter design tool http://focus.ti.com/docs/toolsw/folders/print/filter-designer.html
The filtered audio CW I/Q signals are sampled by audio ADCs and processed by DSP or PC. Although CW
signal frequency is from 20 Hz to 20 KHz, higher sampling rate ADCs are still preferred for further decimation
and SNR enhancement. Due to the large dynamic range of CW signals, high resolution ADCs (>=16bit) are
required, such as ADS8413 (2MSPS/16it/92dBFS SNR) and ADS8472 (1MSPS/16bit/95dBFS SNR). ADCs for
in-phase and quadature-phase channels must be strictly matched, not only amplitude matching but also phase
matching, in order to achieve the best I/Q matching,. In addition, the in-phase and quadrature ADC channels
must be sampled simultaneously.
ADC OPERATION
ADC Clock Configurations
To ensure that the aperture delay and jitter are the same for all channels, the AFE5807 uses a clock tree
network to generate individual sampling clocks for each channel. The clock, for all the channels, are matched
from the source point to the sampling circuit of each of the eight internal ADCs. The variation on this delay is
described in the aperture delay parameter of the output interface timing. Its variation is given by the aperture jitter
number of the same table.
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