TMS320VC5441_15 Datasheet, PDF (61/91 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Functional Overview
Figure 3−30 shows the bit layout of the IMR and the IFR. Table 3−27 describes the bit functions.
15
14
Reserved
13
DMAC5
R/W
12
DMAC4
R/W
11
XINT1 or
DMAC3
R/W
10
RINT1 or
DMAC2
R/W
9
HPINT
R/W
7
6
XINT2 or
DMAC1
RINT2 or
DMAC0
R/W
R/W
LEGEND: R = Read, W = Write
5
XINT0
R/W
4
RINT0
R/W
3
TINT
R/W
2
Reserved
1
WDTINT
R/W
Figure 3−30. Bit Layout of the IMR and IFR Registers for Each Subsystem
8
Reserved
0
INT
R/W
BIT
NO.
15−14
13
12
11
10
9
8
7
6
5
4
Table 3−27. Bit Functions for IMR and IFR Registers for Each DSP Subsystem
BIT
NAME
BIT
VALUE
FUNCTION
Reserved
X
Register bit is reserved.
DMAC5
0
IFR/IMR: DMA Channel 5 has no interrupt pending/is disabled (masked).
1
IFR/IMR: DMA Channel 5 has an interrupt pending/is enabled.
DMAC4
0
IFR/IMR: DMA Channel 4 has no interrupt pending/is disabled (masked).
1
IFR/IMR: DMA Channel 4 has an interrupt pending/is enabled.
XINT1
0
IFR/IMR: McBSP_1 has no transmit interrupt pending/is disabled (masked).
1
IFR/IMR: McBSP_1 has a transmit interrupt pending/is enabled.
DMAC3
0
IFR/IMR: DMA Channel 3 has no interrupt pending/is disabled (masked).
1
IFR/IMR: DMA Channel 3 has an interrupt pending/is enabled.
RINT1
0
IFR/IMR: McBSP_1 has no receive interrupt pending/is disabled (masked).
1
IFR/IMR: McBSP_1 has a receive interrupt pending/is enabled.
DMAC2
0
IFR/IMR: DMA Channel 2 has no interrupt pending/is disabled (masked).
1
IFR/IMR: DMA Channel 2 has an interrupt pending/is enabled.
HPINT
0
IFR/IMR: Host-port interface has no DSPINT interrupt pending/is disabled (masked).
1
IFR/IMR: Host-port interface has an DSPINT interrupt pending/is enabled.
Reserved
X
Register bit is reserved.
XINT2
0
IFR/IMR: McBSP_2 has no transmit interrupt pending/is disabled (masked).
1
IFR/IMR: McBSP_2 has a transmit interrupt pending/is enabled.
DMAC1
0
IFR/IMR: DMA Channel 1 has no interrupt pending/is disabled (masked).
1
IFR/IMR: DMA Channel 1 has an interrupt pending/is enabled.
RINT2
0
IFR/IMR: McBSP_2 has no receive interrupt pending/is disabled (masked).
1
IFR/IMR: McBSP_2 has a receive interrupt pending/is enabled.
DMAC0
0
IFR/IMR: DMA Channel 0 has no interrupt pending/is disabled (masked).
1
IFR/IMR: DMA Channel 0 has an interrupt pending/is enabled.
XINT0
0
IFR/IMR: McBSP_0 has no receive interrupt pending/is disabled (masked).
1
IFR/IMR: McBSP_0 has a receive interrupt pending/is enabled.
RINT0
0
IFR/IMR: McBSP_0 has no receive interrupt pending/is disabled (masked).
1
IFR/IMR: McBSP_0 has a receive interrupt pending/is enabled.
December 1999 − Revised October 2008
SPRS122F
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