TAS3004PFB Datasheet, PDF (61/84 Pages) Texas Instruments – Digital Auido Processor With Codec

8.10 I²C Serial Port Timing Characteristics
MIN MAX UNIT
fscl
tbuf
tlow
thigh
thdsta
tsusta
thddat
tsudat
tr
tf
tsusto
Cb
SCL clock frequency
Bus free time between start and stop
Low period of SCL clock
High period of SCL clock
Hold time repeated start
Setup time repeated start
Data hold time (See Note 6)
Data setup time
Rise time for SDA and SCL
Fall time for SDA and SCL
Setup time for stop condition
Capacitive load for each bus line
0 100 kHz
4.7
µs
4.7
µs
4.0
µs
4.0
µs
4.7
20 µs
0
µs
250
ns
1000 ns
300 ns
4.0
µs
400 pF
NOTE 6: A device must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of
SCL.
PS
P
SDA
Valid
SCL
tBUF
tr
Data
Line
Stable
tHD(DAT)
tsu(DAT)
Change
of Data
Allowed
tsu(STA)
tf
tHD(STA)
NOTE: tlow is measured from the end of tf to the beginning of tr.
thigh is measured from the end of tr to the beginning of tf.
Figure 8–7. I²C Bus Timing
tsu(STO)
tHD(STA)
8–6