DP83816 Datasheet, PDF (60/112 Pages) National Semiconductor (TI) – DP83816 10/100 Mb/s Integrated PCI Ethernet Media Access Controller and Physical Layer (MacPHYTER-II)

DP83816
SNLS164E – SEPTEMBER 2005 – REVISED DECEMBER 2015
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txFragRead
txDescWrite
txAdvance
Waiting for the transfer of a fragment (or portion of a fragment) from the PCI bus to the
TxDataFIFO.
Waiting for the completion of the write of the cmdsts field of an intermediate transmit
descriptor (cmdsts.MORE == 1) to host memory.
(transitory state) Examine the link field of the current descriptor and advance to the next
descriptor if link is not NULL.
The transmit state machine manipulates the following internal data spaces:
TXDP
A 32-bit register that points to the current transmit descriptor.
CTDD
An internal bit flag that is set when the current transmit descriptor has been completed,
and ownership has been returned to the driver. It is cleared whenever TXDP is loaded
with a new value (either by the state machine, or the driver).
TxDescCache An internal data space equal to the size of the maximum transmit descriptor supported.
descCnt
Count of bytes remaining in the current descriptor
fragPtr
Pointer to the next unread byte in the current fragment.
txFifoCnt
Current amount of data in the txDataFifo in bytes.
txFifoAvail
Current amount of free space in the txDataFifo in bytes (size of the txDataFifo –
txFifoCnt).
Inputs to the transmit state machine include the following events:
CR:TXE
XferDone
FifoAvail
Driver asserts the TXE bit in the command register (similar to SONIC).
Completion of a PCI bus transfer request.
TxFifoAvail is greater than TxFillThreshold.
STATE
txIdle
txDescRefr
txDescRead
txFIFOblock
txFragRead
txDescWrite
txAdvance
EVENT
CR:TXE && !CTDD
CR:TXE && CTDD
XferDone
XferDone && OWN
XferDone && !OWN
FifoAvail
(descCnt == 0) &&
MORE
(descCnt == 0) &&
!MORE
XferDone
XferDone
link != NULL
link == NULL
Table 5-9. Transmit State Tables
NEXT STATE
txDescRead
txDescRefr
txAdvance
txFIFOblock
txIdle
txFragRead
txDescWrite
txAdvance
ACTIONS
Start a burst transfer at address TXDP and a length derived from TXCFG.
Start a burst transfer to refresh the link field of the current descriptor.
Set ISR:TXIDLE.
Start a burst transfer into the TxDataFIFO from fragPtr. The length is the
minimum of txFifoAvail and descCnt.
Decrement descCnt accordingly.
Start a burst transfer to write the status back to the descriptor, clearing the
OWN bit.
Write the value of TXDP to the txDataFIFO as a handle.
txFIFOblock
txAdvance
txDescRead
txIdle
TXDP <- txDescCache.link. Clear CTDD. Start a burst transfer at address
TXDP with a length derived from TXCFG.
Set CTDD. Set ISR:TXIDLE. Clear CR:TXE.
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