VFC320_08 Datasheet, PDF (6/11 Pages) Texas Instruments – Voltage-to-Frequency and Frequency-to-Voltage CONVERTER

The operation of the VFC320 as a highly linear frequency-
to-voltage converter, follows the same theory of operation as
the voltage-to-frequency converter. e₁ and e₂ are shorted and
F_IN is disconnected from V_OUT. F_IN is then driven with a
signal which is sufficient to trigger comparator A. The one-
shot period will then be determined by C₁ as before, but the
cycle repetition frequency will be dictated by the digital
input at F_IN.
DUTY CYCLE
The duty cycle (D) of the VFC is the ratio of the one-shot
period (t₂) or pulse width, PW, to the total VFC period (t₁ +
t₂). For the VFC320, t₂ is fixed and t₁ + t₂ varies as the input
voltage. Thus the duty cycle, D, is a function of the input
voltage. Of particular interest is the duty cycle at full scale
frequency, D_FS, which occurs at full scale input. D_FS is a user
determined parameter which affects linearity.
D _FS
=
t₂
t₁ + t₂
=
PW • f_FS
Best linearity is achieved when D_FS is 25%. By reducing
equations (7) and (9) it can be shown that
D_FS = ^{VIN max / R1} = ^{IIN max}
1mA
1mA
Thus D_FS = 0.25 corresponds to I_IN max = 0.25mA.
INSTALLATION AND
OPERATING INSTRUCTIONS
VOLTAGE-TO-FREQUENCY CONVERSION
The VCF320 can be connected to operate as a V/F converter
that will accept either positive or negative input voltages, or
an input current. Refer to Figures 6 and 7.
Gain Adjustment
V_IN
I_IN
1
R₃ R₁
+15V
NC 2
R_{4 NC 3}
R₅
–15V
–V_CC(1) 4
Offset Adj.
One-shot
capacitor
5
C₁
NC 6
+V_PU
7
R_{2 fOUT}
NOTE: (1) Bypass with 0.01µF
C_{2 Integrator Capacitor}
14
Input
Amp
13
12 +V_CC(1)
11
10
One-
shot
9 NC
8 NC
Pin numbers in squares
refer to DIP package.
FIGURE 6. Connection Diagram for V/F Conversion,
Positive Input Voltages.
Gain Adjustment
I_IN
R₁ R₃
+15V
1
NC 2
R_{4 NC 3}
R₅
–15V
–V_CC(1) 4
Offset Adj.
One-shot
Capacitor
5
C₁
NC 6
+V_PU
7
R_{2 fOUT}
NOTE: (1) Bypass with 0.01µF
C_{2 Integrator Capacitor}
V_IN
14
Input
Amp
13
12 +V_CC(1)
11
10
One-
shot
9 NC
8 NC
Pin numbers in squares
refer to DIP package.
FIGURE 7. Connection Diagram for V/F Conversion,
Negative Input Voltages.
EXTERNAL COMPONENT SELECTION
In general, the design sequence consists of: (1) choosing
f_MAX, (2) choosing the duty cycle at full scale (D_FS = 0.25
typically), (3) determining the input resistor, R₁ (Figure 4),
(4) calculating the one-shot capacitor, C₁, (5) selecting the
integrator capacitor C₂, and (6) selecting the output pull-up
resistor, R₂.
Input Resistors R₁ and R₃
The input resistance (R₁ and R₃ in Figures 6 and 7) is
calculated to set the desired input current at full scale input
voltage. This is normally 0.25mA to provide a 25% duty
cycle at full scale input and output. Values other than D_FS =
0.25 may be used but linearity will be affected.
The nominal value is R₁ is
V_INmax
R₁ = _0.25mA
(10)
If gain trimming is to be done, the nominal value is reduced
by the tolerance of C₁ and the desired trim range. R₁ should
have a very-low temperature coefficient since its drift adds
directly to the errors in the transfer function.
One-Shot Capacitor, C₁
This capacitor determines the duration of the one-shot pulse.
From equation (9) the nominal value is
V_IN
C_{1 NOM} = _{7.5 R1 fOUT}
(11)
For the usual 25% duty at f_MAX = V_IN/R₁ = 0.25mA there is
approximately 15pF of residual capacitance so that the
design value is
33 • 10⁶
C₁(pF) =
– 15
f_FS
(12)
6
VFC320
SBVS017A