UCD9240_15 Datasheet, PDF (6/39 Pages) Texas Instruments – Digital PWM System Controller

UCD9240
SLUS766C – JULY 2008 – REVISED NOVEMBER 2008................................................................................................................................................... www.ti.com
HARDWARE FAULT DETECTION LATENCY
The controller contains hardware fault detection circuits that are independent of the ADC monitoring sequencer.
t_FAULT
t_CLF-A
t_CLF-B
PARAMETER
TEST CONDITIONS
Time to disable DPWM output base on active FAULT
pin signal
High level on FAULT pin
Time to disable the DPWM A output based on internal Step change in CS voltage from 0v to
analog comparator
2.5V
Time to disable all remaining DPWM and SRE outputs
configured to drive a voltage rail after a CLF-A event
occurs
Step change in CS voltage from 0V to
2.5V
MAX TIME
15 + 3 ×
NumPhases
4
10 + 3 ×
NumPhases
UNIT
µs
Switch
Cycles
µs
PMBUS/SMBUS/I²C
The timing characteristics and timing diagram for the communications interface that supports I²C, SMBus and
PMBus are shown below.
I²C/SMBus/PMBus Timing Characteristics
T_A = –40°C to 85°C, 3V < V_DD < 3.6V, typical values at T_A = 25°C and V_CC = 2.5 V (Unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
f_SMB
SMBus/PMBus operating frequency
Slave mode; SMBC 50% duty cycle
f_I2C
I C operating frequency
Slave mode; SCL 50% duty cycle
10
1000 kHz
10
1000 kHz
t_(BUF)
t_(HD:STA)
t_(SU:STA)
t_(SU:STO)
t_(HD:DAT)
t_(SU:DAT)
t_(TIMEOUT)
t_(LOW)
t_(HIGH)
t_(LOW:SEXT)
t_FALL
t_RISE
Bus free time between start and stop
Hold time after (repeated) start
Repeated start setup timed
Stop setup time
Data hold time
Data setup time
Error signal/detect
Clock low period
Clock high period
Cumulative clock low slave extend time
Clock/data fall time
Clock/data rise time
Receive mode
See ⁽¹⁾
See ⁽²⁾
See ⁽³⁾
See ⁽⁴⁾
See ⁽⁵⁾
4.7
µs
0.26
µs
0.26
µs
0.26
µs
0
ns
50
ns
35 µs
0.5
µs
0.26
50 µs
25 µs
120 ns
120 ns
(1) The UCD9240 times out when any clock low exceeds t_(TIMEOUT).
(2) t_(HIGH), max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction involving UCD9240 that is
in progress. This specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0]=0).
(3) t_(LOW:SEXT) is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.
(4) Rise time t_RISE = V_VILMAX – 0.15) to (V_VIHMIN + 0.15)
(5) Fall time t_FALL = 0.9 V_DD to (VILMAX – 0.15)
6
Submit Documentation Feedback
Product Folder Link(s): UCD9240
Copyright © 2008, Texas Instruments Incorporated