UCD7242_17 Datasheet, PDF (6/36 Pages) Texas Instruments – Digital Dual Synchronous-Buck Power Driver

UCD7242
SLUS962B – JANUARY 2010 – REVISED AUGUST 2012
www.ti.com
QFN
1
PIN FUNCTIONS
UCD7242 –BUCK POWER STAGE
PIN NAME I/O
FUNCTION
High impedance digital input capable of accepting 3.3V or 5 V logic level signals up to 2 MHz. A
Schmitt trigger input comparator desensitizes this pin from external noise. This pin controls the state of
the high side MOSFET and the low side MOSFET when SRE-B is high.
PWM-B I
SRE = high
SRE = low
PWM = high
HS = on, LS = off
HS = on, LS = off
PWM = low
HS = off, LS = on
HS = off, LS = off
PWM = 1.65 V
HS = off, LS = off
HS = off, LS = off
2
SRE-B
3
BST_B
4
BSW-B
5
V_GG
6
V_GG_DIS
7
IMON-B
8
testmode
9
FLT-B
10, 12, 15, 17
11, 16
13
PGND
NC
SW-B
14
SW-A
18
FLT-A
19
TMON
20
IMON -A
21
GND
22
BP3
23
BSW-A
24
BST-A
Synchronous Rectifier Enable input for the B-channel. High impedance digital input capable of
I accepting 3.3V or 5V logic level signals used to control the synchronous rectifier switch. An appropriate
anti-cross-conduction delay is used during synchronous mode.
I
Connection for the B-channel charge pump capacitor that provides a floating supply for the high side
driver. Connect a 0.22μF ceramic capacitor from this pin to BSW-B (pin 4).
I Connection for B-channel charge pump capacitor. Internally connected to SW-B.
Gate drive voltage for the power MOSFETs. For V_IN ≥ 4.75V, the internal V_GG generator can be used.
I/O
For V_IN < 4.75 V, this pin should be driven from an external bias supply. When externally driven,
V_GG_DIS must be tied to V_GG. In all cases, bypass this pin with a 4.7μF (min), 10V (min) ceramic
capacitor to PGND.
When tied to V_GG, disables the on-chip V_GG generator to allow gate drive voltage to be supplied from
I an external source. This is required when V_IN is < 4.75V. To use the internal V_GG generator, tie to
GND.
MOSFET current sense monitor output. Provides a current source output that is proportional to the
O current flowing in the power MOSFETs. The gain on this pin is equal to 20μA/A. The I_MON pin should
be connected to a resistor to GND to produce a voltage proportional to the power-stage load current.
I Test mode only. Tie to GND.
Fault flag for the B-channel. This signal is a 3.3V digital output which is latched high when the current
in the B-channel high-side FET exceeds the current limit trip point. When tripped, high-side FET drive
O
pulses are truncated to limit output current. FLT is cleared after one complete switching cycle without a
fault. Additionally, if the die temperature exceeds 170°C, the temperature sensor will initiate a thermal
shutdown that halts output switching and sets the FLT flag. Normal operation resumes when the die
temperature falls below the thermal hysteresis band.
– Shared power ground return for the buck power stage
– No internal connection. It is recommended that these pins be tied to PGND.
–
Switching node of the B-channel buck power stage and square wave input to the buck inductor.
Electrically this is the connection of the high side MOSFET source to the low side MOSFET drain.
–
Switching node of the A-channel buck power stage and square wave input to the buck inductor.
Electrically this is the connection of the high side MOSFET source to the low side MOSFET drain.
Fault flag for the A-channel. This signal is a 3.3V digital output which is latched high when the current
in the A-channel high-side FET exceeds the current limit trip point. When tripped, high-side FET drive
O
pulses are truncated to limit output current. FLT is cleared after one complete switching cycle without a
fault. Additionally, if the die temperature exceeds 170°C, the temperature sensor initiates a thermal
shutdown that halts output switching and sets the FLT flag. Normal operation resumes when the die
temperature falls below the thermal hysteresis band.
Temperature sense pin. The voltage on this pin is proportional to the die temperature. The gain is
10mV/°C. At T_J = 0°C, the output voltage has an offset of 0.47V. When the die temperature reaches
O the thermal shutdown threshold, this pin is pulled to BP3 and the power FETs are switched off. When
the die temperature falls below the thermal hysteresis band, the FLT flag clears and normal operation
resumes.
MOSFET current sense monitor output. Provides a current source output that is proportional to the
O current flowing in the power MOSFETs. The gain on this pin is equal to 20μA/A. The IMON pin should
be connected to a resistor to GND to produce a voltage proportional to the power-stage load current.
– Analog ground return.
O
Output of internal 3.3V LDO regulator for powering internal logic circuits. Bypass this pin with 1μF
(min) to GND. This LDO is supplied by the V_GG pin.
– Connection for A-channel charge pump capacitor. Internally connected to SW-A.
–
Connection for the A-channel charge pump capacitor that provides a floating supply for the high side
driver. Connect a 0.22μF ceramic cap from this pin to BSW-A (pin 23).
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