TPS40400 Datasheet, PDF (6/56 Pages) Texas Instruments – 3.0-V TO 20-V PMBus SYNCHRONOUS BUCK CONTROLLER

TPS40400
SLUS930A – APRIL 2011 – REVISED JULY 2011
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ELECTRICAL CHARACTERISTICS (continued)
Unless otherwise stated, these specifications apply for –40°C ≤ T_J ≤ 125°C, V_DD= 12 Vdc, FREQUENCY_SWITCH = 600 kHz
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
OUTPUT VOLTAGE MARGINING
MRG_SLP
VFB slope during margin voltage transition ⁽⁸⁾
Accuracy
V_FBMH
FB pin voltage after margin high command
V_FBML
FB pin voltage after margin low command
V_FBM(max)
Maximum FB pin voltage with Margin
V_FBM(min)
Minimum FB pin voltage with Margin
V_FB(inc)
Resolution of FB steps with margin
OVERVOLTAGE AND UNDERVOLTAGE DETECTION
Factory default settings
3 V < V_VDD < 20 V, 600 μs < t_SS < 9 ms
Factory default settings
Factory default settings
–40°C < T_J < 125°C
–40°C < T_J < 125°C
250
214
–15%
650
660
532
540
742
750
445
450
2.34
188 V/s
15%
670 mV
548 mV
758 mV
455 mV
mV
FB pin overvoltage threshold (OV flag)
V_OV
Accuracy
FB pin undervoltage threshold (UV flag)
V_UV
Accuracy
PMBus INTERFACE
Factory default settings
638
672
3 V < V_VDD < 20 V, 648 mV < V_OV < 690 mV
–5%
Factory default settings
502
528
3 V < V_VDD < 20 V,
510 mV < V_OV < 552 mV
–5%
705
mV
5%
554
mV
5%
V_IH
High-level input voltage, CLK, DATA, CNTL
V_IL
Low-level input voltage, CLK, DATA, CNTL
High-level input current, CLK, DATA, CNTL
I_IH
CNTL
2.1
V
0.8
V
–10
10
μA
–12
10
Low-level input current, CLK, DATA, CNTL
I_IL
CNTL
–10
10
μA
–12
10
V_OL
Low-level output voltage, DATA, SMBALRT
3.0 V ≤ V_VDD ≤ 20 V, I_OUT = 2 mA
I_OH
High-level open drain leakage current, DATA,
SMBALRT
V_OUT = 3.6 V
0.4
V
0
10 μA
C_O ⁽⁸⁾
f_PMB
t_BUF
t_HD:STA
t_SU:STA
t_SU:STO
t_HD:DAT
Pin capacitance, CLK, DATA
PMBus operating frequency range
Bus free time between START and STOP⁽⁸⁾
Hold time after repeated START⁽⁸⁾
Repeated START setup time⁽⁸⁾
STOP setup time⁽⁸⁾
Data hold time⁽⁸⁾
Slave mode
Receive mode
Transmit mode
0.7
10
4.7
4.0
4.7
4.0
0
300
pF
400 kHz
μs
μs
μs
μs
ns
t_SU:DAT
t_TIMEOUT
t_LOW:MEXT
t_LOW:SEXT
t_LOW
t_HIGH
t_FALL
t_RISE
Data setup time⁽⁸⁾
Error signal/detect⁽⁸⁾
Cumulative clock low master extend time⁽⁸⁾
Cumulative clock low slave extend time⁽⁸⁾
Clock low time⁽⁸⁾
Clock high time⁽⁸⁾
CLK/DATA fall time⁽⁸⁾
CLK/DATA rise time⁽⁸⁾
PMBus ADDRESSING
250
ns
25
35 μs
50 μs
25 μs
4.7
μs
4.0
μs
300 ns
1000 ns
I_ADD
V_ADD(L)
ADDX pin current
Address pin illegal low voltage threshold
8.23
9.75
11.21 μA
0.055
V
(8) Ensured by design. Not production tested.
6
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