TLV320AIC3212 Datasheet, PDF (6/61 Pages) Texas Instruments – Ultra Low Power Stereo Audio Codec With Receiver Driver, DirectPath Headphone, and Stereo Class-D Speaker Amplifier

TLV320AIC3212
SLAS784 – MARCH 2012
www.ti.com
WCSP (YZF)
BALL
LOCATION
E8
E9
F1
F2
F3
F4
F5
F6
F7
F8
F9
G1
G2
Table 1. TERMINAL FUNCTIONS – 81 Ball WCSP (YZF) Package (continued)
NAME
SPK_V
SPKRP
IN2L
IN2R
AVDD_18
DVSS
GPI3
GPI2
GPI4
IOVSS
VBAT
MCLK1
BCLK2
I/O/P DESCRIPTION
P Class-D Output Stage Power Supply (Connect to SRVDD through a Resistor)
O Right Channel P side Class-D Output
I Analog Input 2 Left
I Analog Input 2 Right
P 1.8V Analog Power Supply
P Digital Ground
Multi Function Digital Input 3
Primary: (SPI_SELECT = 1)
ADC Bit Clock Input for Audio Serial Data Bus 1, 2, or 3 (Six-Wire Audio
I
Interface)
ADC Word Clock Input for Audio Serial Data Bus 1, 2, or 3 (Six-Wire Audio
Interface)
Secondary: (SPI_SELECT = 0)
I²C Address Bit 1 (I2C_ADDR0, LSB)
Multi Function Digital Input 2
Primary:
General Purpose Input
Secondary:
I
Audio Serial Data Bus 1 Data Input
Digital Microphone Data Input
General Clock Input
Low-Frequency Clock Input
ADC Word Clock Input for Audio Serial Data Bus 1, 2, or 3 (Six-Wire Audio
Interface)
ADC Bit Clock Input for Audio Serial Data Bus 1, 2, or 3 (Six-Wire Audio
Interface)
Multi Function Digital Input 4
Primary: (SPI_SELECT = 1)
ADC Bit Clock Input for Audio Serial Data Bus 1, 2, or 3 (Six-Wire Audio
I
Interface)
ADC Word Clock Input for Audio Serial Data Bus 1, 2, or 3 (Six-Wire Audio
Interface)
Secondary: (SPI_SELECT = 0)
I²C Address Bit 2 (I2C_ADDR1, MSB)
P Digital I/O Buffer Ground
I Battery Monitor Voltage Input
I Master Clock Input 1
Primary:
Audio Serial Data Bus 2 Bit Clock
Secondary:
General Purpose Input
General Purpose Output
I/O
General CLKOUT Output
ADC MOD Clock Output
SAR ADC Interrupt
INT1 Output
INT2 Output
General Clock Input
Low-Frequency Clock Input
6
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