RM48L952 Datasheet, PDF (6/156 Pages) Texas Instruments – RM48L952 16/32-Bit RISC Flash Microcontroller

RM48L952
SPNS177 – SEPTEMBER 2011
1 RM48L952 16/32-Bit RISC Flash Microcontroller
............................................................... 1
1.1 Features .............................................. 1
1.2 Applications .......................................... 2
1.3 Description ........................................... 3
1.4 Functional Block Diagram ............................ 5
1.1 Device Configuration ................................. 7
2 Device Package and Terminal Functions .......... 9
2.2 PGE QFP Package Pinout (144-Pin) ................ 9
2.3 ZWT BGA Package Ball-Map (337 Ball Grid Array)
...................................................... 10
2.4 Terminal Functions ................................. 11
3 Device Operating Conditions ....................... 43
3.1 Absolute Maximum Ratings Over Operating
Free-Air Temperature Range, ...................... 43
3.2 Device Recommended Operating Conditions ...... 43
3.3 Switching Characteristics over Recommended
Operating Conditions for Clock Domains ........... 44
3.4 Wait States Required ............................... 44
3.5 Power Consumption Over Recommended
Operating Conditions ............................... 45
3.6 Input/Output Electrical Characteristics Over
Recommended Operating Conditions .............. 46
3.7 Output Buffer Drive Strengths ...................... 46
3.8 Input Timings ....................................... 47
3.9 Output Timings ..................................... 47
3.10 Low-EMI Output Buffers ............................ 49
4 System Information and Electrical Specifications
............................................................. 50
4.1 Device Power Domains ............................. 50
4.2 Voltage Monitor Characteristics .................... 51
4.3 Power Sequencing and Power On Reset .......... 52
4.4 Warm Reset (nRST) ................................ 54
4.5 ARM^© Cortex-R4F™ CPU Information ............. 55
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4.6 Clocks .............................................. 58
4.7 Clock Monitoring .................................... 66
4.8 Glitch Filters ........................................ 68
4.9 Device Memory Map ................................ 69
4.10 Flash Memory ...................................... 76
4.11 Tightly-Coupled RAM Interface Module ............ 79
4.12 Parity Protection for Accesses to peripheral RAMs
...................................................... 79
4.13 On-Chip SRAM Initialization and Testing ........... 81
4.14 External Memory Interface (EMIF) ................. 83
4.15 Vectored Interrupt Manager ........................ 90
4.16 DMA Controller ..................................... 93
4.17 Real Time Interrupt Module ........................ 96
4.18 Error Signaling Module ............................. 98
4.19 Reset / Abort / Error Sources ..................... 102
4.20 Digital Windowed Watchdog ...................... 104
4.21 Debug Subsystem ................................. 105
5 Peripheral Information and Electrical
Specifications ......................................... 116
5.1 Peripheral Legend ................................. 116
5.2 Multi-Buffered 12bit Analog-to-Digital Converter
..................................................... 116
5.3 General-Purpose Input/Output .................... 125
5.4 Enhanced High-End Timer (N2HET) .............. 126
5.5 Controller Area Network (DCAN) .................. 130
5.6 Local Interconnect Network Interface (LIN) ....... 131
5.7 Serial Communication Interface (SCI) ............ 132
5.8 Inter-Integrated Circuit (I2C) ...................... 133
5.9 Multi-Buffered / Standard Serial Peripheral Interface
..................................................... 136
5.10 Ethernet Media Access Controller ................ 148
5.11 Universal Serial Bus Controller ................... 151
6 Mechanical Data ...................................... 152
6.1 Thermal Data ...................................... 152
6.2 Packaging Information ............................ 152
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