 English |
|
|
|
|
|
|
|
| PCM9211 Datasheet, PDF (6/121 Pages) Texas Instruments – 216-kHz Digital Audio Interface Transceiver (DIX) with Stereo ADC and Routing | |||
| |||
| ◁ |
PCM9211
SBAS495 â JUNE 2010
www.ti.com
ELECTRICAL CHARACTERISTICS: Digital Audio I/F Receiver (DIR)
All specifications at TA = +25°C, VCC = VDD = VDDRX = 3.3 V, and VCCAD = 5 V, unless otherwise noted.
PCM9211
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
DIR, COAXIAL INPUT AMPLIFIER (RXIN0 and RXIN1)
Input resistance
20
kΩ
Input voltage
Input hysteresis
0.2
VPP
50
mV
Input sampling frequency
7
216
kHz
DIR, BIPHASE SIGNAL INPUT and PLL
Input biphase sampling
frequency range
Normal mode
Wide mode
28
108
kHz
7
216
kHz
Input sampling frequency
accuracy
IEC60958-3 (2003-01)
Level III (±12.5%)
Jitter tolerance
IEC60958-3 (2003-01)
IEC60958-3
PLL lock up time(1)
From biphase signal detection to error out
release (ERROR = L)
100
ms
DIR, RECOVERED CLOCK and DATA
Serial audio data width
16
24
Bits
System clock frequency
Bit clock frequency
LR clock frequency
System clock jitter
128fS
256fS
512fS
64fS
fS
fS = 48 kHz, SCKO = 256fS, measured
period jitter
0.896
1.792
3.584
0.448
7
27.648
55.296
55.296
13.824
216
MHz
MHz
MHz
MHz
kHz
50
100 ps, rms
System clock duty cycle
50% reference
±5
±5
%
DIT
Output biphase sampling
frequency
7
216
kHz
128fS
Input system clock frequency 256fS
512fS
Input bit clock frequency
64fS
Input LR clock frequency
fS
OSCILLATOR CIRCUIT, XTI and XMCKO CLOCK
0.896
1.792
3.584
0.448
7
27.648
55.296
55.296
13.824
216
MHz
MHz
MHz
MHz
kHz
XTI source clock frequency
24.576
MHz
Frequency accuracy
â100
100 ppm
XTI input clock duty cycle
45
55
%
XMCKO frequency
24.576
MHz
XMCKO output duty cycle
50% reference
±5
±5
%
PCM OUTPUT PORT (SCKO, BCK, LRCK, DOUT)
System clock frequency
Bit clock output frequency
LR clock output frequency
ROUTING
128fS / 256fS / 512fS
64fS
fS
0.896
0.448
7
55.296
13.824
216
MHz
MHz
kHz
System clock frequency
Bit clock output Frequency
LR clock output frequency
128fS / 256fS / 512fS
64fS
fS
0.896
0.448
7
55.296
13.824
216
MHz
MHz
kHz
(1) PLL lock-up time varies with ERROR release wait time setting (Register 23h/ERRWT). Therefore, lock-up time in this table shows the
value at ERRWT = 11 as the shortest time setting.
6
Submit Documentation Feedback
Product Folder Link(s): PCM9211
Copyright © 2010, Texas Instruments Incorporated
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese