LMK00804B Datasheet, PDF (6/32 Pages) Texas Instruments – Low Skew, 1-to-4 Multiplexed Differential/LVCMOS-to-LVCMOS/TTL Fanout Buffer

LMK00804B
SNAS642A – JUNE 2014 – REVISED JULY 2014
www.ti.com
7.8 Differential Input DC Characteristics
Over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
V_ID
V_ICM
Differential Input Voltage Swing,
(V_IH-V_IL) ⁽¹⁾
Input Common Mode Voltage⁽¹⁾⁽²⁾
0.15
0.5
1.3 V
VDD –
0.85
V
nCLK
I_IH
Input High Current⁽³⁾
CLK
nCLK
I_IL
Input Low Current⁽³⁾
CLK
VDD = 3.465 V,
V_IN = 3.465 V
VDD = 3.465 V,
V_IN = 3.465 V
VDD = 3.465 V ,
V_IN = 0 V
VDD = 3.465 V,
V_IN = 0 V
-150
-5
150
µA
150
µA
(1) V_IL should not be less than -0.3 V.
(2) Input common mode voltage is defined as V_IH.
(3) For I_IH and I_IL measurements on CLK or nCLK, one must comply with V_ID and V_ICM specifications by using the appropriate bias on nCLK
or CLK.
7.9 Electrical Characteristics (VDDO = 3.3 V ± 5%)
Over recommended operating free-air temperature range (unless otherwise noted), VDD = VDDO = 3.3V ± 5%,
All AC parameters measured at ≤ 350 MHz unless otherwise noted.
f_OUT
t_PDLH
t_SK(O)
t_SK(PP)
t_R/t_F
PARAMETER
Maximum Output Frequency⁽¹⁾⁽²⁾
Propagation Delay,
Low to High⁽³⁾
LVCMOS_CLK ⁽⁴⁾,
CLK/nCLK ⁽⁵⁾
Output Skew^(2)(6)(7)
Part-to-Part Skew ^(3)(7)(8)
Output Rise/Fall Time⁽³⁾
J_ADD
Additive Jitter⁽⁹⁾
TEST CONDITIONS
0°C to 70°C
–40°C to 85°C
Measured on rising edge
20% to 80%
f=125 MHz,
Input slew rate ≥ 3 V/ns,
12 kHz to 20 MHz
integration band
MIN
TYP
MAX UNIT
350 MHz
1.1
2.1 ns
0.95
2.2 ns
35 ps
700 ps
50
700 ps
0.04
ps RMS
(1) There is no minimum input / output frequency provided the input slew rate is sufficiently fast. Refer to Input Slew Rate Considerations.
(2) These AC parameters are specified by characterization. Not tested in production.
(3) These AC parameters are specified by design. Not tested in production
(4) Measured from the VDD/2 of the input to the VDDO/2 of the output.
(5) Measured from the differential input crossing point to VDDO/2 of the output.
(6) Defined as skew between outputs at the same supply voltage and with equal loading conditions. Measured at VDDO/2 of the output.
(7) Parameter is defined in accordance with JEDEC Standard 65.
(8) Calculation for part-to-part skew is the difference between the fastest and slowest t_PD across multiple devices, operating at the same
supply voltage, same frequency, same temperature, with equal load conditions, and using the same type of inputs on each device.
(9) Buffer Additive Jitter: J_ADD = SQRT(J_SYSTEM ² - J_SOURCE2), where J_SYSTEM is the RMS jitter of the system output (source+buffer) and
J_SOURCE is the RMS jitter of the input source, and system output noise is not correlated to the input source noise. Additive jitter should
be considered only when the input source noise floor is 3 dB or better than the buffer noise floor (PN_FLOOR). This is usually the case for
high-quality ultra-low-noise oscillators. Please refer to System-Level Phase Noise and Additive Jitter Measurement for input source and
measurement details.
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