DS90CR281 Datasheet, PDF (6/15 Pages) National Semiconductor (TI) – 28-Bit Channel Link

Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
CLHT
CHLT
RCOP
RSKM
Parameter
CMOS/TTL Low-to-High Transition Time (Figure 3)
CMOS/TTL High-to-Low Transition Time (Figure 3)
RxCLK OUT Period (Figure 7)
Receiver Skew Margin (Note 6)
V_CC = 5V, T_A = 25˚C (Figure 17)
RCOH
RxCLK OUT High Time (Figure 7)
RCOL
RxCLK OUT Low Time (Figure 7)
RSRC
RxOUT Setup to RxCLK OUT (Figure 7)
RHRC
RxOUT Hold to RxCLK OUT (Figure 7)
RCCD
RPLLS
RPDD
RxCLK IN to RxCLK OUT Delay @ 25˚C,
V_CC = 5.0V (Figure 9)
Receiver Phase Lock Loop Set (Figure 11)
Receiver Powerdown Delay (Figure 15 )
f = 20 MHz
f = 40 MHz
f = 20 MHz
f = 40 MHz
f = 20 MHz
f = 40 MHz
f = 20 MHz
f = 40 MHz
f = 20 MHz
f = 40 MHz
Min
Typ
Max
Units
3.5
6.5
ns
2.7
6.5
ns
25
T
50
ns
1.1
ns
700
ps
19
ns
6
ns
21.5
ns
10.5
ns
14
ns
4.5
ns
16
ns
6.5
ns
7.6
11.9
ns
10
ms
1
µs
Note 6: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account for transmitter output skew (TCCS)
and the setup and hold time (internal data sampling window), allowing LVDS cable skew dependent on the type/length and source clock (TxCLK IN) jitter.
RSKM ≥ cable skew (type, length) + source clock jitter (cycle to cycle).
AC Timing Diagrams
FIGURE 1. “WORST CASE” Test Pattern
DS012638-4
DS012638-5
FIGURE 2. DS90CR281 (Transmitter) LVDS Output Load and Transition Timing
DS012638-6
5
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