DRV8301-Q1 Datasheet, PDF (6/28 Pages) Texas Instruments – AUTOMOTIVE THREE PHASE PRE-DRIVER WITH DUAL CURRENT SHUNT AMPLIFIERS

DRV8301-Q1
SLOS842 – SEPTEMBER 2013
www.ti.com
ABSOLUTE MAXIMUM RATINGS⁽¹⁾
PVDD
PVDD_RAMP
V_PGND
I_{IN_MAX}
I_{IN_OD_MAX}
V_{OPA_IN}
V_LOGIC
V_GVDD
V_AVDD
V_DVDD
V_{VDD_SPI}
V_SDO
V_REF
I_REF
T_J
T_STORAGE
Supply voltage range including transient Relative to PGND
Maximum supply voltage ramp rate
Voltage rising up to PVDD_MAX
Maximum voltage between PGND and GND
Maximum current, all digital and analog input pins except FAULT and OCTW pins
Maximum sinking current for open drain pins (FAULT and OCTW Pins)
Voltage range for SPx and SNx pins
Input voltage range for logic/digital pins (INH_A, INL_A, INH_B, INL_B, INH_C,
INL_C, EN_GATE, SCLK, SDI, SCS, DC_CAL)
Maximum voltage for GVDD Pin
Maximum voltage for AVDD Pin
Maximum voltage for DVDD Pin
Maximum voltage for VDD_SPI Pin
Maximum voltage for SDO Pin
Maximum reference voltage for current amplifier
Maximum current for REF Pin
Maximum operating junction temperature range
Storage temperature range
Capacitive discharge model
Human body model
VALUE
MIN
–0.3
±0.3
±1
7
±0.6
-0.3
MAX
70
1
7
UNITS
V
V/µs
V
mA
mA
V
V
13.2
V
8
V
3.6
V
7
V
VDD_SPI +0.3
V
7
V
100
µA
–40
150
°C
–55
150
°C
Per AEC-Q100
Per AEC-Q100
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
THERMAL INFORMATION
THERMAL METRIC⁽¹⁾
DRV8301-Q1
DCA
UNITS
θ_JA
θ_JCtop
θ_JB
ψ_JT
ψ_JB
θ_JCbot
Junction-to-ambient thermal resistance⁽²⁾
Junction-to-case (top) thermal resistance⁽³⁾
Junction-to-board thermal resistance⁽⁴⁾
Junction-to-top characterization parameter⁽⁵⁾
Junction-to-board characterization parameter⁽⁶⁾
Junction-to-case (bottom) thermal resistance⁽⁷⁾
56 PINS
30.3
33.5
17.5
0.9
7.2
0.9
°C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ_JA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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