DAC7551-Q1_15 Datasheet, PDF (6/27 Pages) Texas Instruments – 12-Bit, Ultra-Low Glitch, Voltage Output Digital-to-Analog Converter

DAC7551-Q1
SLAS767B – JUNE 2011 – REVISED MARCH 2015
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6.6 Timing Requirements⁽¹⁾
All specifications at –40°C to +105°C, V_DD = 2.7 to 5.5 V, and R_L = 2 kΩ to GND (unless otherwise noted). See Figure 1.
MIN
MAX UNIT
t₁ ⁽²⁾
SCLK cycle time
t₂
SCLK HIGH time
t₃
SCLK LOW time
t₄
SYNC falling edge to SCLK falling edge setup time
t₅
Data setup time
t₆
Data hold time
t₇
SCLK falling edge to SYNC rising edge
t₈
Minimum SYNC HIGH time
t₉
SCLK falling edge to SDO valid
t₁₀
CLR pulse width low
V_DD = 2.7 V to 3.6 V
V_DD = 3.6 V to 5.5 V
V_DD = 2.7 V to 3.6 V
V_DD = 3.6 V to 5.5 V
V_DD = 2.7 V to 3.6 V
V_DD = 3.6 V to 5.5 V
V_DD = 2.7 V to 3.6 V
V_DD = 3.6 V to 5.5 V
V_DD = 2.7 V to 3.6 V
V_DD = 3.6 V to 5.5 V
V_DD = 2.7 V to 3.6 V
V_DD = 3.6 V to 5.5 V
V_DD = 2.7 V to 3.6 V
V_DD = 3.6 V to 5.5 V
V_DD = 2.7 V to 3.6 V
V_DD = 3.6 V to 5.5 V
V_DD = 2.7 V to 3.6 V
V_DD = 3.6 V to 5.5 V
V_DD = 2.7 V to 3.6 V
V_DD = 3.6 V to 5.5 V
20
ns
20
6.5
ns
6.5
6.5
ns
6.5
4
ns
4
3
ns
3
3
ns
3
0 t₁ – 10 ns⁽³⁾
0 t₁ – 10 ns⁽³⁾
ns
20
ns
20
10
ns
10
10
ns
10
(1) All input signals are specified with t_R = t_F = 1 ns (10% to 90% of V_DD) and timed from a voltage level of (V_IL + V_IH) / 2.
(2) Maximum SCLK frequency is 50 MHz at V_DD = 2.7 to 5.5 V.
(3) SCLK falling edge to SYNC rising edge time shold not exceed (t₁ – 10 ns) to latch the correct data.
t₁
SCLK
t₈
t₄
t₃
t₂
t₇
SYNC
t₅
t₆
SDIN
D15
D14 D13
D12
D11
D1
D0
D15
D0
SDO
Input Word n
t₉ ^{Input Word n+1}
D15
D14
D0
CLR
Undefined
t₁₀
Input Word n
Figure 1. Serial Write Operation Timing Diagram
6
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