ADS8422 Datasheet, PDF (6/29 Pages) Burr-Brown (TI) – 16-BIT, 4-MSPS, PSEUDO-BIPOLAR, FULLY DIFFERENTIAL INPUT, MICROPOWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE, REFERENCE

ADS8422
SLAS512B – JUNE 2006 – REVISED DECEMBER 2006
www.ti.com
TIMING CHARACTERISTICS FROM DIGITAL INPUTS
All specifications typical at –40°C to 85°C, +VBD = 2.7 V to 5.25 V ⁽¹⁾⁽²⁾
PARAMETER
CONVERSION AND ACQUISITION
t_(ACQ) Acquisition time, internal to device, not externally visible
t_w1
Pulse duration, CONVST low
t_w2
Pulse duration, CONVST high
t_p1
Period, CONVST
t_q1
Quiet time, last toggle of interface input signals during acquisition before CONVST falling ⁽³⁾
t_q2
Quiet time, CONVST falling to first toggle of interface input signals ⁽³⁾
POWER DOWN
PD1 low for only ADC reset (no powerdown)
t_w3
Pulse duration PD1 low for ADC reset and also ADC powerdown
PD2 low pulse duration for REFOUT and COMMOUT buffers powerdown
Pulse duration, all others unspecified
MIN TYP MAX UNIT
70
ns
20
ns
100
ns
250
ns
30
ns
10
ns
20
1500
1500
10
500
ns
ns
(1) All input signals are specified with t_r = t_f = 5 ns (10% to 90% of V_DD) and timed from after 90% of transition.
(2) All digital output signals loaded with 10-pF capacitors at +VBD = 2.7 V and 20-pF capacitor at +VBD = 5.25 V and timed to reaching
90% of transition.
(3) Quiet time zones are for meeting performance and not functionality.
TIMING CHARACTERISTICS OF DIGITAL OUTPUTS
All specifications typical at –40°C to 85°C, +VBD = 2.7 V to 5.25 V ⁽¹⁾⁽²⁾
PARAMETER
CONVERSION AND ACQUISITION
t_(CONV) Conversion time, internal to device, not externally visible
t_d1
Delay time, CONVST fall to conversion start (aperture delay)
DATA READ OPERATION
t_d2
Delay time, CONVST low to data valid if CS = RD = 0
t_d3
Delay time, data valid to BUSY low if CS = RD = 0
t_d4
Delay time, RD (or CS) low to data valid
t_d5
Delay time, BYTE toggle to data valid
t_d6
Delay time, data three-state after RD (or CS) high
POWER DOWN
t_d7
Delay time, PD1 low to BUSY rising
Delay time, PD1 high to device operational (with PD2 held high)
t_d8
Delay time, PD2 high to REFOUT/COMMOUT valid
Delay time, power up (after AV_DD = 4.75 V)
t_d9
Delay time, data three-state after PD1 low
MIN TYP
3
5
MAX UNIT
180 ns
ns
225 ns
ns
17 ns
20 ns
12 ns
20 ns
5 µs
25 ms
25 ms
1.5 µs
(1) All input signals are specified with t_r = t_f = 5 ns (10% to 90% of V_DD) and timed from after 90% of transition.
(2) All digital output signals loaded with 10-pF capacitors at +VBD = 2.7 V and 20-pF capacitor at +VBD = 5.25 V and timed to reaching
90% of transition.
6
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