ADS5521 Datasheet, PDF (6/36 Pages) Burr-Brown (TI) – 12-Bit, 105MSPS Analog-toDigital Converter

ADS5521
SBAS309D – MAY 2004 – REVISED OCTOBER 2008 ...................................................................................................................................................... www.ti.com
TIMING CHARACTERISTICS⁽¹⁾⁽²⁾
Typical values given at T_A = 25°C, min and max specified over the full recommended operating temperature range, AV_DD =
DRV_DD = 3.3 V, sampling rate = 105MSPS, 50% clock duty cycle, 3-V_PP differential clock, and C_LOAD = 10 pF, unless
otherwise noted⁽¹⁾
PARAMETER
Switching Specification
Aperture delay, t_A
Aperture jitter (uncertainty)
Data setup time, t_SETUP
Data hold time, t_HOLD
Input clock to output data valid start,
t_START ^{(4) (5)}
Input clock to output data valid end,
t_END ^{(4) (5)}
Output clock jitter, t_JIT
Output clock rise time, t_r
Output clock fall time, t_f
Input clock to output clock delay, t_PDI
Data rise time, t_r
Data fall time, t_f
Output enable(OE) to data output delay
Wakeup time
Latency
DESCRIPTION
Input CLK falling edge to data sampling point
Uncertainty in sampling instant
Data valid⁽³⁾ to 50% of CLKOUT rising edge
50% of CLKOUT rising edge to data becoming
invalid ⁽³⁾
Input clock rising edge to data valid start delay
Input clock rising edge to data valid end delay
Uncertainty in CLKOUT rising edge, peak-to-peak
Rise time of CLKOUT from 20% to 80% of DRV_DD
Fall time of CLKOUT from 80% to 20% of DRV_DD
Input clock rising edge, zero crossing, to output
clock rising edge 50%
Data rise time measured from 20% to 80% of
DRV_DD
Data fall time measured from 80% to 20% of
DRV_DD
Time required for outputs to have stable timings
with regard to input clock⁽⁶⁾ after OE is activated
Time to valid data after coming out of software
power down
Time to valid data after stopping and restarting the
clock
Time for a sample to propagate to the ADC outputs
MIN
TYP
MAX UNIT
1
ns
300
fs
2.2
2.8
ns
2.2
2.5
ns
1.9
2.8 ns
5.8
7.3
ns
175
250 ps_PP
2
2.2 ns
1.7
1.8 ns
4
4.7
5.5 ns
4.4
5.1 ns
3.3
3.8 ns
1000
1000
1000
Clock
cycles
Clock
cycles
17.5
Clock
cycles
(1) Timing parameters are ensured by design and characterization, and not tested in production.
(2) See Table 6 through Table 9 in the Application Information section for timing information at additional sampling frequencies.
(3) Data valid refers to 2 V for LOGIC HIGH and 0.8 V for LOGIC LOW.
(4) See the Output Information section for details on using the input clock for data capture.
(5) These specifications apply when the CLKOUT polarity is set to rising edge (according to Table 3). Add 1/2 clock period for the valid
number for a falling edge CLKOUT polarity.
(6) Data outputs are available within a clock from assertion of OE; however, it takes 1000 clock cycles to ensure stable timing with respect
to input clock.
6
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