ADS5444 Datasheet, PDF (6/29 Pages) Texas Instruments – 13-BIT 250 MSPS ANALOG-TO-DIGITAL CONVERTER

ADS5444
SLWS162A – AUGUST 2005 – REVISED FEBRUARY 2006
TIMING CHARACTERISTICS
t_A
N
N+3
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AIN
CLK, CLK
D[12:0],
OVR, OVR
DRY, DRY
N+1
N+2
t_CLK
N
t_CLKH
N+1
t_CLKL
N+2
t_{C_DR}
N−3
N−2
t_r
t_f
t_{su_DR}
N+3
N−1
t_{h_DR}
N+4
N+4
t_{su_c}
t_{h_c}
N
t_DR
Figure 1. Timing Diagram
T0073-01
TIMING CHARACTERISTICS
Min, Typ, Max over full temperature range, 50% clock duty cycle, sampling rate = 250 MSPS, AV_DD = 5 V, DRV_DD = 3.3 V
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
t_A
Aperature delay
t_J
Clock slope independent aperture uncertainty (jitter)
Latency
500
ps
200
fs RMS
4
cycles
Clock Input
t_CLK
Clock period
t_CLKH
Clock pulsewidth high
t_CLKL
Clock pulsewidth low
Clock to DataReady (DRY)
4
ns
2
ns
2
ns
t_DR
Clock rising to DataReady falling
t_{C_DR}
Clock rising to DataReady rising
Clock to DATA, OVR⁽²⁾
Clock duty cycle = 50% ⁽¹⁾
1.1
2.7 3.1
ns
3.5 ns
t_r
Data rise time (20% to 80%)
t_f
Data fall time(80% to 20%)
t_{su_c}
Data valid to clock (setup time)
t_{h_c}
Clock to invalid Data (hold time)
DataReady (DRY)/DATA, OVR⁽²⁾
0.6
ns
0.6
ns
3.1
ns
0.2
ns
t_su(DR)
t_h(DR)
Data valid to DRY
DRY to invalid Data
1.7
2
ns
0.9 1.3
ns
(1) t_{C_DR} = t_DR + t_CLKH for clock duty cycles other than 50%
(2) Data is updated with clock falling edge or DRY rising edge.
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