ADS5204-Q1 Datasheet, PDF (6/25 Pages) Texas Instruments – DUAL 10-BIT 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER WITH PGA

ADS5204ĆQ1
SGLS271A − OCTOBER 2004 − REVISED JUNE 2008
PIN CONFIGURATION
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Terminal Functions
TERMINAL
NAME
NO.
I/O
DRV_DD
1,13
I
DRV_SS
12, 24 I
DA 9..0
14-23 O
DB 9..0
2-11 O
OE
C_OUT
C_OUT
SDI
DV_SS
CLK
DV_DD
AV_DD
CS
AV_SS
B−
B+
REFT
48
I
26
O
25
O
44
I
43
I
47
I
45
I
27,37,41 I
29
I
28,36,40 I
35
I
34
I
31
I/O
REFB
30
I/O
CML
32
O
PDWN_REF
33
I
STBY
42
I
A−
39
I
A+
38
I
SCLK
46
I
DESCRIPTION
Supply Voltage for Output Drivers
Digital Ground for Output Drivers
Data Outputs for Bus A. D9 is MSB. This is the primary bus. Data from both input channels can be output on this bus
or data from channel A only. The data outputs are in 3-state during power-down (see the Register Configuration table).
Data Outputs for Bus B. D9 is MSB. This is the second bus. Data is output from the B channel when dual bus output
mode is selected. The data outputs are in 3-state during power-down and single-bus modes (see the Timing Options
table).
Output Enable. A low on this terminal will enable the data output bus, C_OUT and C_OUT.
Latch Clock for the Data Outputs. C_OUT is in 3-state during power down.
Inverted Latch Clock control for the Data Outputs. C_OUT is in 3-state during power down.
Serial Data I/O
Digital Ground
Clock Input. The input is sampled on each rising edge of CLK when using a 40-MHz input and alternate rising edges
when using an 80-MHz input. The clock pin is referenced to AV_DD and AV_SS to reduce noise coupling from digital logic.
Digital Supply Voltage
Analog Supply Voltage
Serial Data Registers Chip Select
Analog Ground
Negative Input for the Analog B Channel
Positive Input for the Analog B Channel
Reference Voltage Top. The voltage at this terminal defines the top reference voltage for the ADC. Sufficient filtering
should be applied to this input: the use of 0.1-µF capacitor between REFT and AV_SS is highly recommended.
Additionally a 0.1-µF capacitor should be connected between REFT and REFB.
Reference Voltage Bottom. The voltage at this terminal defines the bottom reference voltage for the ADC. Sufficient
filtering should be applied to this input: the use of 0.1-µF capacitor between REFB and AV_SS is recommended.
Additionally, a 0.1-µF capacitor should be connected between REFT and REFB.
Common-Mode Level. This voltage is equal to (AV_DD − AV_SS)/2. An external capacitor of 0.1µF should be connected
between this terminal and AV_SS when CML is used as a bias voltage. No capacitor is required if CML is not used.
Power-Down for Internal Reference Voltages. A HIGH on this terminal disables the internal reference circuit.
Standby Input. A high on this terminal powers down the device.
Negative Input for the Analog A Channel
Positive Input for Analog A Channel
Serial Data Clock. Maximum clock rate is 20 MHz.
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