ADC102S101_14 Datasheet, PDF (6/28 Pages) Texas Instruments – ADC102S101 2 Channel, 500 ksps to 1 Msps, 10-Bit A/D Converter

ADC102S101
SNAS287G – FEBRUARY 2005 – REVISED MARCH 2013
www.ti.com
ADC102S101 Timing Specifications
The following specifications apply for V_A = +2.7V to 5.25V, GND = 0V, C_L = 50 pF, f_SCLK = 8 MHz to 16 MHz,
f_SAMPLE = 500 ksps to 1 Msps, Boldface limits apply for T_A = T_MIN to T_MAX:
all other limits T_A = 25°C.
Symbol
Parameter
Conditions
Typical Limits⁽¹⁾
Units
t_CSU Setup Time SCLK High to CS Falling Edge
t_CLH Hold time SCLK Low to CS Falling Edge
t_EN Delay from CS Until DOUT active
t_ACC Data Access Time after SCLK Falling Edge
t_SU Data Setup Time Prior to SCLK Rising Edge
t_H
Data Valid SCLK Hold Time
t_CH SCLK High Pulse Width
t_CL SCLK Low Pulse Width
t_DIS CS Rising Edge to DOUT High-Impedance
See ⁽²⁾
See ⁽²⁾
V_A = +3.0V
V_A = +5.0V
V_A = +3.0V
V_A = +5.0V
V_A = +3.0V
V_A = +5.0V
V_A = +3.0V
V_A = +5.0V
Output Falling
Output Rising
V_A = +3.0V
V_A = +5.0V
V_A = +3.0V
V_A = +5.0V
−3.5
10
ns (min)
−0.5
+4.5
10
ns (min)
+1.5
+4
30
ns (max)
+2
+16.5
+15
30
ns (max)
+3
10
ns (min)
+3
10
ns (min)
0.5 x t_SCLK
0.5 x t_SCLK
1.7
0.3 x t_SCLK
0.3 x t_SCLK
ns (min)
ns (min)
1.2
20
ns (max)
1
1
(1) Tested limits are guaranteed to TI's AOQL (Average Outgoing Quality Level).
(2) Clock may be either high or low when CS is asserted as long as setup and hold times t_CSU and t_CLH are strictly observed.
6
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