ADC10065_15 Datasheet, PDF (6/26 Pages) Texas Instruments – 10-Bit 65 MSPS 3V A/D Converter

ADC10065
SNAS225H – JULY 2003 – REVISED APRIL 2013
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Converter Electrical Characteristics
Unless otherwise specified, the following specifications apply for V_SSA = V_SSIO = 0V, V_DDA = +3.0V, V_DDIO = +2.5V, V_IN = 2 V_P-P,
STBY = 0V, V_REF = 1.20V (External), f_CLK = 65 MHz, 50% Duty Cycle, C_L = 10 pF/pin. Boldface limits apply for T_A = T_MIN to
T_MAX: all other limits T_A = 25°C. ^(1)(2)(3)(4).
Parameter
Test Conditions
Min
Typ
Max
Units
STATIC CONVERTER CHARACTERISTICS
No Missing Codes ensured
10
Bits
INL
Integral Non-Linearity
F_IN = 500 kHz, −0 dB Full
Scale
−1.0
±0.3
+1.1
LSB
DNL
Differential Non-Linearity
F_IN = 500 kHz, −0 dB Full
Scale
−0.9
±0.3
+0.9
LSB
GE
Gain Error
Positive Error
Negative Error
−1.5
−1.5
+0.4
+0.03
+1.9
+1.9
% FS
% FS
OE
Offset Error (V_IN+ = V_IN−)
Under Range Output Code
−1.4
0.2
+1.7
% FS
0
FPBW
Over Range Output Code
Full Power Bandwidth ⁽⁵⁾
1023
400
MHz
REFERENCE AND INPUT CHARACTERISTICS
V_CM
V_COM
Common Mode Input Voltage
Output Voltage for use as an input
common mode voltage ⁽⁶⁾
0.5
1.5
V
1.45
V
V_REF
V_REFTC
Reference Voltage
Reference Voltage Temperature
Coefficient
1.2
V
±80
ppm/°C
C_IN
V_IN Input Capacitance (each pin to
V_SSA)
POWER SUPPLY CHARACTERISTICS
4
pF
I_VDDA
Analog Supply Current
STBY = 1
STBY = 0
4.7
6.0
mA
22
29
mA
I_VDDIO
PWR
Digital Supply Current ⁽⁷⁾
Power Consumption ⁽⁸⁾
STBY = 1, f_IN = 0 Hz
STBY 0, f_IN = 0 Hz
STBY = 1
STBY = 0
0
mA
0.97
1.2
mA
14.1
18.0
mW
68.4
90
mW
(1) To ensure accuracy, it is required that |V_DDA–V_DDIO| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.
(2) With the test condition for 2 V_P-P differential input, the 10-bit LSB is 1.95 mV.
(3) Typical figures are at T_A = T_J = 25°C and represent most likely parametric norms. Test limits are specified to Texas Instrument's AOQL
(Average Outgoing Quality Level).
(4) The analog inputs are protected as shown below. Input voltage magnitude up to 500 mV beyond the supply rails will not damage this
device. However, input errors will be generated if the input goes above V_DDA or V_DDIO and below V_SSA or V_SSIO. See Figure 2
(5) The input bandwidth is limited using a capacitor between V_IN^− and V_IN+.
(6) VCOM is a typical value, measured at room temperature. It is not specified by test. Do not load this pin.
(7) I_DDIO is the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins,
the supply voltage, V_DR, and the rate at which the outputs are switching (which is signal dependent). I_DR = V_DR x (C₀ x f₀ + C₁ x f₁ + C₂
+ f₂ +....C₁₁ x f₁₁) where V_DR is the output driver supply voltage, C_n is the total load capacitance on the output pin, and f_n is the average
frequency at which the pin is toggling.
(8) Power consumption includes output driver power. (f_IN = 0 MHz).
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